#if HAS_TICK
++ao_tick_count;
#endif
-#if HAS_TASK_QUEUE
- if (ao_task_alarm_tick && (int16_t) (ao_tick_count - ao_task_alarm_tick) >= 0)
- ao_task_check_alarm((uint16_t) ao_tick_count);
-#endif
+ ao_task_check_alarm();
#if AO_DATA_ALL
- if (++ao_data_count == ao_data_interval) {
+ if (++ao_data_count == ao_data_interval && ao_data_interval) {
ao_data_count = 0;
#if HAS_FAKE_FLIGHT
if (ao_fake_flight_active)
cfgr |= (AO_RCC_CFGR_PPRE2_DIV << STM_RCC_CFGR_PPRE2);
stm_rcc.cfgr = cfgr;
+ /* Clock configuration register DCKCFGR2; mostly make sure USB
+ * gets clocked from PLL_Q
+ */
+ stm_rcc.dckcfgr2 = ((STM_RCC_DCKCFGR2_LPTIMER1SEL_APB << STM_RCC_DCKCFGR2_LPTIMER1SEL) |
+ (STM_RCC_DCKCFGR2_SDIOSEL_CK_48MHZ << STM_RCC_DCKCFGR2_SDIOSEL) |
+ (STM_RCC_DCKCFGR2_CK48MSEL_PLL_Q << STM_RCC_DCKCFGR2_CK48MSEL) |
+ (STM_RCC_DCKCFGR2_I2CFMP1SEL_APB << STM_RCC_DCKCFGR2_I2CFMP1SEL));
+
/* Disable the PLL */
stm_rcc.cr &= ~(1 << STM_RCC_CR_PLLON);
while (stm_rcc.cr & (1 << STM_RCC_CR_PLLRDY))
pllcfgr |= (AO_PLL_M << STM_RCC_PLLCFGR_PLLM);
pllcfgr |= (AO_PLL1_N << STM_RCC_PLLCFGR_PLLN);
-#if AO_PLL1_P
#if AO_PLL1_P == 2
#define AO_RCC_PLLCFGR_PLLP STM_RCC_PLLCFGR_PLLP_DIV_2
#endif
#define AO_RCC_PLLCFGR_PLLP STM_RCC_PLLCFGR_PLLP_DIV_8
#endif
pllcfgr |= (AO_RCC_PLLCFGR_PLLP << STM_RCC_PLLCFGR_PLLP);
-#endif
-#if AO_PLL1_Q
pllcfgr |= (AO_PLL1_Q << STM_RCC_PLLCFGR_PLLQ);
-#endif
-#if AO_PLL1_R
pllcfgr |= (AO_PLL1_R << STM_RCC_PLLCFGR_PLLR);
-#endif
/* PLL source */
pllcfgr &= ~(1 << STM_RCC_PLLCFGR_PLLSRC);
#if AO_HSI
#if DEBUG_THE_CLOCK
/* Output PLL clock on PA8 and SYCLK on PC9 for measurments */
- stm_rcc.ahb1enr |= ((1 << STM_RCC_AHB1ENR_IOPAEN) |
- (1 << STM_RCC_AHB1ENR_IOPCEN));
-
+ ao_enable_port(&stm_gpioa);
stm_afr_set(&stm_gpioa, 8, STM_AFR_AF0);
stm_moder_set(&stm_gpioa, 8, STM_MODER_ALTERNATE);
stm_ospeedr_set(&stm_gpioa, 8, STM_OSPEEDR_HIGH);
+ ao_enable_port(&stm_gpioc);
stm_afr_set(&stm_gpioc, 9, STM_AFR_AF0);
stm_moder_set(&stm_gpioc, 9, STM_MODER_ALTERNATE);
stm_ospeedr_set(&stm_gpioc, 9, STM_OSPEEDR_HIGH);