uint8_t mosi_dma_index = ao_spi_stm_info[AO_SPI_INDEX(spi_index)].mosi_dma_index;
uint8_t miso_dma_index = ao_spi_stm_info[AO_SPI_INDEX(spi_index)].miso_dma_index;
+ spi_dev_null = 0xff;
+
/* Set up transmit DMA to make the SPI hardware actually run */
ao_dma_set_transfer(mosi_dma_index,
&stm_spi->dr,
case STM_SPI_INDEX(1):
switch (spi_index) {
case AO_SPI_1_PA5_PA6_PA7:
- stm_gpio_set(&stm_gpioa, 5, 0);
+ stm_gpio_set(&stm_gpioa, 5, 1);
stm_moder_set(&stm_gpioa, 5, STM_MODER_OUTPUT);
stm_moder_set(&stm_gpioa, 6, STM_MODER_INPUT);
stm_moder_set(&stm_gpioa, 7, STM_MODER_OUTPUT);
break;
case AO_SPI_1_PB3_PB4_PB5:
- stm_gpio_set(&stm_gpiob, 3, 0);
+ stm_gpio_set(&stm_gpiob, 3, 1);
stm_moder_set(&stm_gpiob, 3, STM_MODER_OUTPUT);
stm_moder_set(&stm_gpiob, 4, STM_MODER_INPUT);
stm_moder_set(&stm_gpiob, 5, STM_MODER_OUTPUT);
break;
case AO_SPI_1_PE13_PE14_PE15:
- stm_gpio_set(&stm_gpioe, 13, 0);
+ stm_gpio_set(&stm_gpioe, 13, 1);
stm_moder_set(&stm_gpioe, 13, STM_MODER_OUTPUT);
stm_moder_set(&stm_gpioe, 14, STM_MODER_INPUT);
stm_moder_set(&stm_gpioe, 15, STM_MODER_OUTPUT);
case STM_SPI_INDEX(2):
switch (spi_index) {
case AO_SPI_2_PB13_PB14_PB15:
- stm_gpio_set(&stm_gpiob, 13, 0);
+ stm_gpio_set(&stm_gpiob, 13, 1);
stm_moder_set(&stm_gpiob, 13, STM_MODER_OUTPUT);
stm_moder_set(&stm_gpiob, 14, STM_MODER_INPUT);
stm_moder_set(&stm_gpiob, 15, STM_MODER_OUTPUT);
break;
case AO_SPI_2_PD1_PD3_PD4:
- stm_gpio_set(&stm_gpiod, 1, 0);
+ stm_gpio_set(&stm_gpiod, 1, 1);
stm_moder_set(&stm_gpiod, 1, STM_MODER_OUTPUT);
stm_moder_set(&stm_gpiod, 3, STM_MODER_INPUT);
stm_moder_set(&stm_gpiod, 4, STM_MODER_OUTPUT);
#if HAS_SPI_1
# if SPI_1_PA5_PA6_PA7
stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIOAEN);
+ stm_ospeedr_set(&stm_gpioa, 5, SPI_1_OSPEEDR);
+ stm_ospeedr_set(&stm_gpioa, 6, SPI_1_OSPEEDR);
+ stm_ospeedr_set(&stm_gpioa, 7, SPI_1_OSPEEDR);
# endif
# if SPI_1_PB3_PB4_PB5
stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIOBEN);
+ stm_ospeedr_set(&stm_gpiob, 3, SPI_1_OSPEEDR);
+ stm_ospeedr_set(&stm_gpiob, 4, SPI_1_OSPEEDR);
+ stm_ospeedr_set(&stm_gpiob, 5, SPI_1_OSPEEDR);
# endif
# if SPI_1_PE13_PE14_PE15
stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIOEEN);
+ stm_ospeedr_set(&stm_gpioe, 13, SPI_1_OSPEEDR);
+ stm_ospeedr_set(&stm_gpioe, 14, SPI_1_OSPEEDR);
+ stm_ospeedr_set(&stm_gpioe, 15, SPI_1_OSPEEDR);
# endif
stm_rcc.apb2enr |= (1 << STM_RCC_APB2ENR_SPI1EN);
ao_spi_index[0] = AO_SPI_CONFIG_NONE;
#if HAS_SPI_2
# if SPI_2_PB13_PB14_PB15
stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIOBEN);
+ stm_ospeedr_set(&stm_gpiob, 13, SPI_2_OSPEEDR);
+ stm_ospeedr_set(&stm_gpiob, 14, SPI_2_OSPEEDR);
+ stm_ospeedr_set(&stm_gpiob, 15, SPI_2_OSPEEDR);
# endif
# if SPI_2_PD1_PD3_PD4
stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIODEN);
+ stm_ospeedr_set(&stm_gpiod, 1, SPI_2_OSPEEDR);
+ stm_ospeedr_set(&stm_gpiod, 3, SPI_2_OSPEEDR);
+ stm_ospeedr_set(&stm_gpiod, 4, SPI_2_OSPEEDR);
# endif
stm_rcc.apb1enr |= (1 << STM_RCC_APB1ENR_SPI2EN);
ao_spi_index[1] = AO_SPI_CONFIG_NONE;