#if AO_PCLK1 == 16000000
# define AO_STM_I2C_CR2_FREQ STM_I2C_CR2_FREQ_16_MHZ
#endif
+#if AO_PCLK1 == 24000000
+# define AO_STM_I2C_CR2_FREQ STM_I2C_CR2_FREQ_24_MHZ
+#endif
#if AO_PCLK1 == 32000000
# define AO_STM_I2C_CR2_FREQ STM_I2C_CR2_FREQ_32_MHZ
#endif
ao_wakeup(&ao_i2c_state[index]);
}
if (sr1 & (1 << STM_I2C_SR1_RXNE)) {
- if (ao_i2c_recv_len[index]) {
+ if (ao_i2c_recv_len[index]) {
*(ao_i2c_recv_data[index]++) = stm_i2c->dr;
if (!--ao_i2c_recv_len[index])
ao_wakeup(&ao_i2c_recv_len[index]);
(0 << STM_DMA_CCR_PINC) |
(0 << STM_DMA_CCR_CIRC) |
(STM_DMA_CCR_DIR_MEM_TO_PER << STM_DMA_CCR_DIR));
-
+
ao_dma_start(tx_dma_index);
ao_arch_block_interrupts();
while (!ao_dma_done[tx_dma_index])
block,
len,
(0 << STM_DMA_CCR_MEM2MEM) |
- (STM_DMA_CCR_PL_MEDIUM << STM_DMA_CCR_PL) |
+ (STM_DMA_CCR_PL_HIGH << STM_DMA_CCR_PL) |
(STM_DMA_CCR_MSIZE_8 << STM_DMA_CCR_MSIZE) |
(STM_DMA_CCR_PSIZE_8 << STM_DMA_CCR_PSIZE) |
(1 << STM_DMA_CCR_MINC) |