* Improved support for STM32L152RE - flash/ram sizes, now correct, flash programming...

[fw/stlink] / src / stlink-common.h

diff --git a/src/stlink-common.h b/src/stlink-common.h
index 8430fc55d21463b55c6759fae597b17a5567ecfe..cce4d9f3e512ef3413f88de1ef6151cbf3492aef 100644 (file)
--- a/src/stlink-common.h
+++ b/src/stlink-common.h
@@ -117,12 +117,14 @@ extern "C" {
  * 0x436 HIGH.
  */
 #define STM32_CHIPID_L1_HIGH 0x436
+#define STM32_CHIPID_L152_RE 0x437
 #define STM32_CHIPID_F1_CONN 0x418
 #define STM32_CHIPID_F1_VL_MEDIUM 0x420
 #define STM32_CHIPID_F1_VL_HIGH 0x428
 #define STM32_CHIPID_F1_XL 0x430
 #define STM32_CHIPID_F0 0x440
 #define STM32_CHIPID_F0_SMALL 0x444
+#define STM32_CHIPID_F0_CAN 0x448
 
 // Constant STM32 memory map figures
 #define STM32_FLASH_BASE 0x08000000
@@ -252,7 +254,15 @@ static const chip_params_t devices[] = {
                     .bootrom_base = 0x1ff00000,
                     .bootrom_size = 0x1000
         },
-
+        {
+            .chip_id = STM32_CHIPID_L152_RE,
+                    .description = "L152RE",
+                    .flash_size_reg = 0x1ff800cc,
+                    .flash_pagesize = 0x100,
+                    .sram_size = 0x14000, /*Not completely clear if there are some with 32K*/
+                    .bootrom_base = 0x1ff00000,
+                    .bootrom_size = 0x1000
+        },
         {
             .chip_id = STM32_CHIPID_F1_CONN,
                     .description = "F1 Connectivity line device",
@@ -311,6 +321,17 @@ static const chip_params_t devices[] = {
                     .bootrom_base = 0x1fffe000,
                     .bootrom_size = 0x1800
         },
+        { 
+             //Use this as an example for mapping future chips:
+             //RM0091 document was used to find these paramaters
+            .chip_id = STM32_CHIPID_F0_CAN,
+                    .description = "F07x device",
+                    .flash_size_reg = 0x1ffff7cc,      // "Flash size data register" (pg735)
+                    .flash_pagesize = 0x800,           // Page sizes listed in Table 4
+                    .sram_size = 0x4000,               // "SRAM" byte size in hex from Table 2
+                    .bootrom_base = 0x1fffC800,                // "System memory" starting address from Table 2
+                    .bootrom_size = 0x3000             // "System memory" byte size in hex from Table 2
+        },
         {
             //Use this as an example for mapping future chips:
             //RM0091 document was used to find these paramaters