* Improved support for STM32L152RE - flash/ram sizes, now correct, flash programming...

[fw/stlink] / src / stlink-common.h

diff --git a/src/stlink-common.h b/src/stlink-common.h
index 579622892b38ccb4858a50636f454f0537003663..cce4d9f3e512ef3413f88de1ef6151cbf3492aef 100644 (file)
--- a/src/stlink-common.h
+++ b/src/stlink-common.h
@@ -1,7 +1,7 @@
-/* 
+/*
  * File:   stlink-common.h
  * Bulk import from stlink-hw.h
- * 
+ *
  * This should contain all the common top level stlink interfaces, regardless
  * of how the backend does the work....
  */
@@ -24,6 +24,7 @@ extern "C" {
 #define USB_ST_VID                     0x0483
 #define USB_STLINK_PID                 0x3744
 #define USB_STLINK_32L_PID             0x3748
+#define USB_STLINK_NUCLEO_PID  0x374b
 
     // STLINK_DEBUG_RESETSYS, etc:
 #define STLINK_OK                      0x80
@@ -67,7 +68,7 @@ extern "C" {
 #define STLINK_DEBUG_WRITEDEBUGREG     0x0f
 #define STLINK_DEBUG_ENTER_SWD         0xa3
 #define STLINK_DEBUG_ENTER_JTAG        0x00
-    
+
     // TODO - possible poor names...
 #define STLINK_SWD_ENTER 0x30
 #define STLINK_SWD_READCOREID 0x32  // TBD
@@ -105,6 +106,7 @@ extern "C" {
 #define STM32_CHIPID_F4 0x413
 #define STM32_CHIPID_F4_HD 0x419
 #define STM32_CHIPID_F4_LP 0x423
+#define STM32_CHIPID_F4_DE 0x433
 #define STM32_CHIPID_F1_HIGH 0x414
 #define STM32_CHIPID_L1_MEDIUM 0x416
 #define STM32_CHIPID_L1_MEDIUM_PLUS 0x427
@@ -115,12 +117,14 @@ extern "C" {
  * 0x436 HIGH.
  */
 #define STM32_CHIPID_L1_HIGH 0x436
+#define STM32_CHIPID_L152_RE 0x437
 #define STM32_CHIPID_F1_CONN 0x418
 #define STM32_CHIPID_F1_VL_MEDIUM 0x420
 #define STM32_CHIPID_F1_VL_HIGH 0x428
 #define STM32_CHIPID_F1_XL 0x430
 #define STM32_CHIPID_F0 0x440
 #define STM32_CHIPID_F0_SMALL 0x444
+#define STM32_CHIPID_F0_CAN 0x448
 
 // Constant STM32 memory map figures
 #define STM32_FLASH_BASE 0x08000000
@@ -144,8 +148,8 @@ extern "C" {
        uint32_t sram_size;
        uint32_t bootrom_base, bootrom_size;
     } chip_params_t;
-    
-    
+
+
 // These maps are from a combination of the Programming Manuals, and
 // also the Reference manuals.  (flash size reg is normally in ref man)
 static const chip_params_t devices[] = {
@@ -161,7 +165,7 @@ static const chip_params_t devices[] = {
         {  // table 1, PM0059
             .chip_id = STM32_CHIPID_F2,
                     .description = "F2 device",
-                    .flash_size_reg = 0x1ff7a22, /* RM0033 sind Rev 4*/
+                    .flash_size_reg = 0x1fff7a22, /* As in RM0033 Rev 5*/
                     .flash_pagesize = 0x20000,
                     .sram_size = 0x20000,
                     .bootrom_base = 0x1fff0000,
@@ -203,6 +207,15 @@ static const chip_params_t devices[] = {
                     .bootrom_base = 0x1fff0000,
                     .bootrom_size = 0x7800
         },
+        {
+            .chip_id = STM32_CHIPID_F4_DE,
+                    .description = "F4 device (Dynamic Efficency)",
+                    .flash_size_reg = 0x1FFF7A22,
+                    .flash_pagesize = 0x4000,
+                    .sram_size = 0x18000,
+                    .bootrom_base = 0x1fff0000,
+                    .bootrom_size = 0x7800
+        },
         {
             .chip_id = STM32_CHIPID_F1_HIGH,
                     .description = "F1 High-density device",
@@ -241,7 +254,15 @@ static const chip_params_t devices[] = {
                     .bootrom_base = 0x1ff00000,
                     .bootrom_size = 0x1000
         },
-
+        {
+            .chip_id = STM32_CHIPID_L152_RE,
+                    .description = "L152RE",
+                    .flash_size_reg = 0x1ff800cc,
+                    .flash_pagesize = 0x100,
+                    .sram_size = 0x14000, /*Not completely clear if there are some with 32K*/
+                    .bootrom_base = 0x1ff00000,
+                    .bootrom_size = 0x1000
+        },
         {
             .chip_id = STM32_CHIPID_F1_CONN,
                     .description = "F1 Connectivity line device",
@@ -300,6 +321,17 @@ static const chip_params_t devices[] = {
                     .bootrom_base = 0x1fffe000,
                     .bootrom_size = 0x1800
         },
+        { 
+             //Use this as an example for mapping future chips:
+             //RM0091 document was used to find these paramaters
+            .chip_id = STM32_CHIPID_F0_CAN,
+                    .description = "F07x device",
+                    .flash_size_reg = 0x1ffff7cc,      // "Flash size data register" (pg735)
+                    .flash_pagesize = 0x800,           // Page sizes listed in Table 4
+                    .sram_size = 0x4000,               // "SRAM" byte size in hex from Table 2
+                    .bootrom_base = 0x1fffC800,                // "System memory" starting address from Table 2
+                    .bootrom_size = 0x3000             // "System memory" byte size in hex from Table 2
+        },
         {
             //Use this as an example for mapping future chips:
             //RM0091 document was used to find these paramaters
@@ -324,7 +356,7 @@ static const chip_params_t devices[] = {
         },
  };
 
-    
+
     typedef struct {
         uint32_t r[16];
         uint32_t s[32];
@@ -341,7 +373,7 @@ static const chip_params_t devices[] = {
     } reg;
 
     typedef uint32_t stm32_addr_t;
-    
+
     typedef struct _cortex_m3_cpuid_ {
         uint16_t implementer_id;
         uint16_t variant;
@@ -431,7 +463,7 @@ static const chip_params_t devices[] = {
 #define STM32L_SRAM_SIZE (16 * 1024)
         stm32_addr_t sram_base;
         size_t sram_size;
-        
+
         // bootloader
         stm32_addr_t sys_base;
         size_t sys_size;
@@ -476,7 +508,7 @@ static const chip_params_t devices[] = {
     int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr);
     int stlink_fwrite_sram(stlink_t *sl, const char* path, stm32_addr_t addr);
     int stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, uint32_t length);
-    
+
     // PUBLIC
     uint32_t stlink_chip_id(stlink_t *sl);
     void stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid);
@@ -502,7 +534,7 @@ static const chip_params_t devices[] = {
 
 
 #include "stlink-sg.h"
-#include "stlink-usb.h"    
+#include "stlink-usb.h"