// Max data transfer size.
// 6kB = max mem32_read block, 8kB sram
//#define Q_BUF_LEN 96
-#define Q_BUF_LEN 1024 * 100
+#define Q_BUF_LEN (1024 * 100)
// st-link vendor cmd's
#define USB_ST_VID 0x0483
#define USB_STLINK_PID 0x3744
+#define USB_STLINK_32L_PID 0x3748
// STLINK_DEBUG_RESETSYS, etc:
#define STLINK_OK 0x80
#define STLINK_DEBUG_COMMAND 0xF2
#define STLINK_DFU_COMMAND 0xF3
#define STLINK_DFU_EXIT 0x07
+ // enter dfu could be 0x08?
// STLINK_GET_CURRENT_MODE
#define STLINK_DEV_DFU_MODE 0x00
#define STLINK_DEBUG_WRITEDEBUGREG 0x0f
#define STLINK_DEBUG_ENTER_SWD 0xa3
#define STLINK_DEBUG_ENTER_JTAG 0x00
+
+ // TODO - possible poor names...
+#define STLINK_SWD_ENTER 0x30
+#define STLINK_SWD_READCOREID 0x32 // TBD
+
+// cortex m3 technical reference manual
+#define CM3_REG_CPUID 0xE000ED00
+#define CM3_REG_FP_CTRL 0xE0002000
+#define CM3_REG_FP_COMP0 0xE0002008
+
+/* Enough space to hold both a V2 command or a V1 command packaged as generic scsi*/
+#define C_BUF_LEN 32
typedef struct {
uint32_t r[16];
} reg;
typedef uint32_t stm32_addr_t;
+
+ typedef struct _cortex_m3_cpuid_ {
+ uint16_t implementer_id;
+ uint16_t variant;
+ uint16_t part;
+ uint8_t revision;
+ } cortex_m3_cpuid_t;
+
+ typedef struct stlink_version_ {
+ uint32_t stlink_v;
+ uint32_t jtag_v;
+ uint32_t swim_v;
+ uint32_t st_vid;
+ uint32_t stlink_pid;
+ } stlink_version_t;
+
+ typedef struct flash_loader {
+ stm32_addr_t loader_addr; /* loader sram adddr */
+ stm32_addr_t buf_addr; /* buffer sram address */
+ } flash_loader_t;
enum transport_type {
TRANSPORT_TYPE_ZERO = 0,
};
typedef struct _stlink stlink_t;
-
+
typedef struct _stlink_backend {
- void (*close) (stlink_t* sl);
- void (*exit_debug_mode) (stlink_t *sl);
- void (*enter_swd_mode) (stlink_t *sl);
- void (*enter_jtag_mode) (stlink_t *stl);
- void (*exit_dfu_mode) (stlink_t *stl);
- void (*core_id) (stlink_t *stl);
- void (*reset) (stlink_t *stl);
- void (*run) (stlink_t *stl);
- void (*status) (stlink_t *stl);
- void (*version) (stlink_t *stl);
+ void (*close) (stlink_t * sl);
+ void (*exit_debug_mode) (stlink_t * sl);
+ void (*enter_swd_mode) (stlink_t * sl);
+ void (*enter_jtag_mode) (stlink_t * stl);
+ void (*exit_dfu_mode) (stlink_t * stl);
+ void (*core_id) (stlink_t * stl);
+ void (*reset) (stlink_t * stl);
+ void (*run) (stlink_t * stl);
+ void (*status) (stlink_t * stl);
+ void (*version) (stlink_t *sl);
+ void (*read_mem32) (stlink_t *sl, uint32_t addr, uint16_t len);
void (*write_mem32) (stlink_t *sl, uint32_t addr, uint16_t len);
void (*write_mem8) (stlink_t *sl, uint32_t addr, uint16_t len);
+ void (*read_all_regs) (stlink_t *sl, reg * regp);
+ void (*read_reg) (stlink_t *sl, int r_idx, reg * regp);
+ void (*write_reg) (stlink_t *sl, uint32_t reg, int idx);
+ void (*step) (stlink_t * stl);
+ int (*current_mode) (stlink_t * stl);
+ void (*force_debug) (stlink_t *sl);
} stlink_backend_t;
struct _stlink {
struct _stlink_backend *backend;
void *backend_data;
+ // Room for the command header
+ unsigned char c_buf[C_BUF_LEN];
// Data transferred from or to device
unsigned char q_buf[Q_BUF_LEN];
int q_len;
uint32_t core_id;
int core_stat;
-
-
+
+
/* medium density stm32 flash settings */
#define STM32_FLASH_BASE 0x08000000
#define STM32_FLASH_SIZE (128 * 1024)
void DD(stlink_t *sl, char *format, ...);
//stlink_t* stlink_quirk_open(const char *dev_name, const int verbose);
-
+
// delegated functions...
void stlink_enter_swd_mode(stlink_t *sl);
void stlink_enter_jtag_mode(stlink_t *sl);
void stlink_exit_debug_mode(stlink_t *sl);
void stlink_exit_dfu_mode(stlink_t *sl);
void stlink_close(stlink_t *sl);
- void stlink_core_id(stlink_t *sl);
+ uint32_t stlink_core_id(stlink_t *sl);
void stlink_reset(stlink_t *sl);
void stlink_run(stlink_t *sl);
void stlink_status(stlink_t *sl);
void stlink_version(stlink_t *sl);
+ void stlink_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len);
void stlink_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len);
void stlink_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len);
-
-
- // unprocessed
+ void stlink_read_all_regs(stlink_t *sl, reg *regp);
+ void stlink_read_reg(stlink_t *sl, int r_idx, reg *regp);
+ void stlink_write_reg(stlink_t *sl, uint32_t reg, int idx);
+ void stlink_step(stlink_t *sl);
int stlink_current_mode(stlink_t *sl);
void stlink_force_debug(stlink_t *sl);
- void stlink_step(stlink_t *sl);
- void stlink_read_all_regs(stlink_t *sl);
- void stlink_read_reg(stlink_t *sl, int r_idx);
- void stlink_write_reg(stlink_t *sl, uint32_t reg, int idx);
- void stlink_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len);
- int stlink_erase_flash_page(stlink_t* sl, stm32_addr_t page);
+
+ // unprocessed
int stlink_erase_flash_mass(stlink_t* sl);
int stlink_write_flash(stlink_t* sl, stm32_addr_t address, uint8_t* data, unsigned length);
+ int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr);
+
+ // PUBLIC
+ uint16_t stlink_chip_id(stlink_t *sl);
+ void stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid);
- // privates....
+ // privates, publics, the rest....
+ // TODO sort what is private, and what is not
+ int stlink_erase_flash_page(stlink_t* sl, stm32_addr_t page);
uint16_t read_uint16(const unsigned char *c, const int pt);
void stlink_core_stat(stlink_t *sl);
void stlink_print_data(stlink_t *sl);
unsigned int is_bigendian(void);
+ uint32_t read_uint32(const unsigned char *c, const int pt);
+ void write_uint32(unsigned char* buf, uint32_t ui);
+ void write_uint16(unsigned char* buf, uint16_t ui);
+ unsigned int is_core_halted(stlink_t *sl);
+ int write_buffer_to_sram(stlink_t *sl, flash_loader_t* fl, const uint8_t* buf, size_t size);
+ int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size);
+ int stlink_fread(stlink_t* sl, const char* path, stm32_addr_t addr, size_t size);
+ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, const uint8_t* buf, size_t size);
+
#include "stlink-sg.h"