#define STM32_CHIPID_F1_HIGH 0x414
#define STM32_CHIPID_L1_MEDIUM 0x416
-
+#define STM32_CHIPID_L0 0x417
#define STM32_CHIPID_F1_CONN 0x418
#define STM32_CHIPID_F4_HD 0x419
-#define STM32_CHIPID_F1_VL_MEDIUM 0x420
+#define STM32_CHIPID_F1_VL_MEDIUM_LOW 0x420
+#define STM32_CHIPID_F446 0x421
#define STM32_CHIPID_F3 0x422
#define STM32_CHIPID_F4_LP 0x423
+#define STM32_CHIPID_F411RE 0x431
+
#define STM32_CHIPID_L1_MEDIUM_PLUS 0x427
#define STM32_CHIPID_F1_VL_HIGH 0x428
+#define STM32_CHIPID_L1_CAT2 0x429
#define STM32_CHIPID_F1_XL 0x430
#define STM32_CHIPID_L1_HIGH 0x436
#define STM32_CHIPID_L152_RE 0x437
-
+#define STM32_CHIPID_F334 0x438
#define STM32_CHIPID_F3_SMALL 0x439
#define STM32_CHIPID_F0 0x440
-
+#define STM32_CHIPID_F09X 0x442
#define STM32_CHIPID_F0_SMALL 0x444
+#define STM32_CHIPID_F04 0x445
+
+#define STM32_CHIPID_F303_HIGH 0x446
+
#define STM32_CHIPID_F0_CAN 0x448
/*
.description = "F42x and F43x device",
.flash_size_reg = 0x1FFF7A22, /* As in rm0090 since Rev 2*/
.flash_pagesize = 0x4000,
- .sram_size = 0x30000,
+ .sram_size = 0x40000,
.bootrom_base = 0x1fff0000,
.bootrom_size = 0x7800
},
.bootrom_base = 0x1fff0000,
.bootrom_size = 0x7800
},
+ {
+ .chip_id = STM32_CHIPID_F411RE,
+ .description = "F4 device (low power) - stm32f411re",
+ .flash_size_reg = 0x1FFF7A22,
+ .flash_pagesize = 0x4000,
+ .sram_size = 0x20000,
+ .bootrom_base = 0x1fff0000,
+ .bootrom_size = 0x7800
+ },
{
.chip_id = STM32_CHIPID_F4_DE,
.description = "F4 device (Dynamic Efficency)",
.bootrom_base = 0x1ff00000,
.bootrom_size = 0x1000
},
+ {
+ .chip_id = STM32_CHIPID_L1_CAT2,
+ .description = "L1 Cat.2 device",
+ .flash_size_reg = 0x1ff8004c,
+ .flash_pagesize = 0x100,
+ .sram_size = 0x8000,
+ .bootrom_base = 0x1ff00000,
+ .bootrom_size = 0x1000
+ },
{
.chip_id = STM32_CHIPID_L1_MEDIUM_PLUS,
.description = "L1 Medium-Plus-density device",
.bootrom_base = 0x1fffb000,
.bootrom_size = 0x4800
},
- {
- .chip_id = STM32_CHIPID_F1_VL_MEDIUM,
- .description = "F1 Medium-density Value Line device",
+ {//Low and Medium density VL have same chipid. RM0041 25.6.1
+ .chip_id = STM32_CHIPID_F1_VL_MEDIUM_LOW,
+ .description = "F1 Medium/Low-density Value Line device",
.flash_size_reg = 0x1ffff7e0,
.flash_pagesize = 0x400,
- .sram_size = 0x2000,
+ .sram_size = 0x2000,//0x1000 for low density devices
.bootrom_base = 0x1ffff000,
.bootrom_size = 0x800
},
+ {
+ // STM32F446x family. Support based on DM00135183.pdf (RM0390) document.
+ .chip_id = STM32_CHIPID_F446,
+ .description = "F446 device",
+ .flash_size_reg = 0x1fff7a22,
+ .flash_pagesize = 0x20000,
+ .sram_size = 0x20000,
+ .bootrom_base = 0x1fff0000,
+ .bootrom_size = 0x7800
+ },
{
// This is STK32F303VCT6 device from STM32 F3 Discovery board.
// Support based on DM00043574.pdf (RM0316) document.
.bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2
.bootrom_size = 0xC00 // "System memory" byte size in hex from Table 2
},
+ {
+ .chip_id = STM32_CHIPID_F09X,
+ .description = "F09X device",
+ .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735)
+ .flash_pagesize = 0x800, // Page sizes listed in Table 4 (pg 56)
+ .sram_size = 0x8000, // "SRAM" byte size in hex from Table 2 (pg 50)
+ .bootrom_base = 0x1fffd800, // "System memory" starting address from Table 2
+ .bootrom_size = 0x2000 // "System memory" byte size in hex from Table 2
+ },
+ {
+ //Use this as an example for mapping future chips:
+ //RM0091 document was used to find these paramaters
+ .chip_id = STM32_CHIPID_F04,
+ .description = "F04x device",
+ .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735)
+ .flash_pagesize = 0x400, // Page sizes listed in Table 4
+ .sram_size = 0x1800, // "SRAM" byte size in hex from Table 2
+ .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2
+ .bootrom_size = 0xC00 // "System memory" byte size in hex from Table 2
+ },
{
//Use this as an example for mapping future chips:
//RM0091 document was used to find these paramaters
.bootrom_base = 0x1fffd800,
.bootrom_size = 0x2000
},
- };
+ {
+ // STM32L0x
+ // RM0367,RM0377 documents was used to find these parameters
+ .chip_id = STM32_CHIPID_L0,
+ .description = "L0x3 device",
+ .flash_size_reg = 0x1ff8007c,
+ .flash_pagesize = 0x80,
+ .sram_size = 0x2000,
+ .bootrom_base = 0x1ff0000,
+ .bootrom_size = 0x1000
+ },
+ {
+ // STM32F334
+ // RM0364 document was used to find these parameters
+ .chip_id = STM32_CHIPID_F334,
+ .description = "F334 device",
+ .flash_size_reg = 0x1ffff7cc,
+ .flash_pagesize = 0x800,
+ .sram_size = 0x3000,
+ .bootrom_base = 0x1fffd800,
+ .bootrom_size = 0x2000
+ },
+ {
+ // This is STK32F303RET6 device from STM32 F3 Nucelo board.
+ // Support based on DM00043574.pdf (RM0316) document rev 5.
+ .chip_id = STM32_CHIPID_F303_HIGH,
+ .description = "F303 high density device",
+ .flash_size_reg = 0x1ffff7cc, // 34.2.1 Flash size data register
+ .flash_pagesize = 0x800, // 4.2.1 Flash memory organization
+ .sram_size = 0x10000, // 3.3 Embedded SRAM
+ .bootrom_base = 0x1fffd800, // 3.3.2 / Table 4 System Memory
+ .bootrom_size = 0x2000
+ },
+
+ };
typedef struct {
projects / fw / stlink / blobdiff