Support arm core cpuid register decoding

[fw/stlink] / src / stlink-common.h

diff --git a/src/stlink-common.h b/src/stlink-common.h
index 3e5d461fe154c2b41de6c955986608378e658d1d..b357c7a52a533438aa68f61b2a4d2ab1a049295d 100644 (file)
--- a/src/stlink-common.h
+++ b/src/stlink-common.h
@@ -23,6 +23,7 @@ extern "C" {
     // st-link vendor cmd's
 #define USB_ST_VID                     0x0483
 #define USB_STLINK_PID                 0x3744
+#define USB_STLINK_32L_PID             0x3748
 
     // STLINK_DEBUG_RESETSYS, etc:
 #define STLINK_OK                      0x80
@@ -37,6 +38,7 @@ extern "C" {
 #define STLINK_DEBUG_COMMAND           0xF2
 #define STLINK_DFU_COMMAND             0xF3
 #define STLINK_DFU_EXIT                0x07
+    // enter dfu could be 0x08?
 
     // STLINK_GET_CURRENT_MODE
 #define STLINK_DEV_DFU_MODE            0x00
@@ -64,6 +66,13 @@ extern "C" {
 #define STLINK_DEBUG_WRITEDEBUGREG     0x0f
 #define STLINK_DEBUG_ENTER_SWD         0xa3
 #define STLINK_DEBUG_ENTER_JTAG        0x00
+    
+    // TODO - possible poor names...
+#define STLINK_SWD_ENTER 0x30
+#define STLINK_SWD_READCOREID 0x32  // TBD
+
+// cortex m3 technical reference manual
+#define CM3_REG_CPUID 0xE000ED00
 
     typedef struct {
         uint32_t r[16];
@@ -75,6 +84,21 @@ extern "C" {
     } reg;
 
     typedef uint32_t stm32_addr_t;
+    
+    typedef struct _cortex_m3_cpuid_ {
+        uint16_t implementer_id;
+        uint16_t variant;
+        uint16_t part;
+        uint8_t revision;
+    } cortex_m3_cpuid_t;
+
+    typedef struct stlink_version_ {
+        uint32_t stlink_v;
+        uint32_t jtag_v;
+        uint32_t swim_v;
+        uint32_t st_vid;
+        uint32_t stlink_pid;
+    } stlink_version_t;
 
     typedef struct flash_loader {
         stm32_addr_t loader_addr; /* loader sram adddr */
@@ -100,15 +124,16 @@ extern "C" {
         void (*reset) (stlink_t * stl);
         void (*run) (stlink_t * stl);
         void (*status) (stlink_t * stl);
-        void (*version) (stlink_t * stl);
+        void (*version) (stlink_t *sl);
         void (*read_mem32) (stlink_t *sl, uint32_t addr, uint16_t len);
         void (*write_mem32) (stlink_t *sl, uint32_t addr, uint16_t len);
         void (*write_mem8) (stlink_t *sl, uint32_t addr, uint16_t len);
-        void (*read_all_regs) (stlink_t *sl, reg* regp);
-        void (*read_reg) (stlink_t *sl, int r_idx, reg* regp);
+        void (*read_all_regs) (stlink_t *sl, reg * regp);
+        void (*read_reg) (stlink_t *sl, int r_idx, reg * regp);
         void (*write_reg) (stlink_t *sl, uint32_t reg, int idx);
         void (*step) (stlink_t * stl);
         int (*current_mode) (stlink_t * stl);
+        void (*force_debug) (stlink_t *sl);
     } stlink_backend_t;
 
     struct _stlink {
@@ -160,7 +185,7 @@ extern "C" {
     void stlink_exit_debug_mode(stlink_t *sl);
     void stlink_exit_dfu_mode(stlink_t *sl);
     void stlink_close(stlink_t *sl);
-    void stlink_core_id(stlink_t *sl);
+    uint32_t stlink_core_id(stlink_t *sl);
     void stlink_reset(stlink_t *sl);
     void stlink_run(stlink_t *sl);
     void stlink_status(stlink_t *sl);
@@ -173,13 +198,16 @@ extern "C" {
     void stlink_write_reg(stlink_t *sl, uint32_t reg, int idx);
     void stlink_step(stlink_t *sl);
     int stlink_current_mode(stlink_t *sl);
+    void stlink_force_debug(stlink_t *sl);
 
 
     // unprocessed
-    void stlink_force_debug(stlink_t *sl);
-
     int stlink_erase_flash_mass(stlink_t* sl);
     int stlink_write_flash(stlink_t* sl, stm32_addr_t address, uint8_t* data, unsigned length);
+    
+    // PUBLIC
+    uint16_t stlink_chip_id(stlink_t *sl);
+    void stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid);
 
     // privates, publics, the rest....
     // TODO sort what is private, and what is not