Merge branch 'master' of https://github.com/texane/stlink

[fw/stlink] / src / stlink-common.h

diff --git a/src/stlink-common.h b/src/stlink-common.h
index 0379753b98dd27656337939542a6ba4dfa63850d..aeeaa85a4778e3eb7cc57e15a0a00bfbc6793b2f 100644 (file)
--- a/src/stlink-common.h
+++ b/src/stlink-common.h
@@ -132,6 +132,8 @@ extern "C" {
 
 #define STM32_CHIPID_F0_SMALL       0x444
 
+#define STM32_CHIPID_F04            0x445
+
 #define STM32_CHIPID_F0_CAN         0x448
 
     /*
@@ -209,7 +211,7 @@ extern "C" {
             .description = "F42x and F43x device",
             .flash_size_reg = 0x1FFF7A22,  /* As in rm0090 since Rev 2*/
             .flash_pagesize = 0x4000,
-            .sram_size = 0x30000,
+            .sram_size = 0x40000,
             .bootrom_base = 0x1fff0000,
             .bootrom_size = 0x7800
         },
@@ -367,6 +369,17 @@ extern "C" {
             .bootrom_base = 0x1fffec00,                // "System memory" starting address from Table 2
             .bootrom_size = 0xC00              // "System memory" byte size in hex from Table 2
         },
+        {
+            //Use this as an example for mapping future chips:
+            //RM0091 document was used to find these paramaters
+            .chip_id = STM32_CHIPID_F04,
+            .description = "F04x device",
+            .flash_size_reg = 0x1ffff7cc,      // "Flash size data register" (pg735)
+            .flash_pagesize = 0x400,           // Page sizes listed in Table 4
+            .sram_size = 0x1000,               // "SRAM" byte size in hex from Table 2
+            .bootrom_base = 0x1fffec00,                // "System memory" starting address from Table 2
+            .bootrom_size = 0xC00              // "System memory" byte size in hex from Table 2
+        },
         {
             //Use this as an example for mapping future chips:
             //RM0091 document was used to find these paramaters