Merge pull request #370 from brunowonka/STM32L4_flash_fix

[fw/stlink] / src / stlink-common.h

diff --git a/src/stlink-common.h b/src/stlink-common.h
index 3fceeef62fe8807f5d6ce53de35b53441c1b6316..a0bd64909d5b4f6fd9a7c7e22fb2880cca35fe78 100644 (file)
--- a/src/stlink-common.h
+++ b/src/stlink-common.h
@@ -124,6 +124,9 @@ extern "C" {
 
 #define STM32_CHIPID_F37x           0x432
 #define STM32_CHIPID_F4_DE          0x433
+#define STM32_CHIPID_F4_DE          0x433
+
+#define STM32_CHIPID_F4_DSI         0x434
 
 #define STM32_CHIPID_L1_HIGH        0x436
 #define STM32_CHIPID_L152_RE        0x437
@@ -140,6 +143,8 @@ extern "C" {
 
 #define STM32_CHIPID_F0_CAN         0x448
 
+#define STM32_CHIPID_F7             0x449
+
     /*
      * 0x436 is actually assigned to some L1 chips that are called "Medium-Plus"
      * and some that are called "High".  0x427 is assigned to the other "Medium-
@@ -174,6 +179,16 @@ extern "C" {
     // These maps are from a combination of the Programming Manuals, and
     // also the Reference manuals.  (flash size reg is normally in ref man)
     static const chip_params_t devices[] = {
+        {
+            //RM0385 and DS10916 document was used to find these paramaters
+            .chip_id = STM32_CHIPID_F7,
+            .description = "F7 device",
+            .flash_size_reg = 0x1ff0f442,      // section 41.2
+            .flash_pagesize = 0x800,           // No flash pages
+            .sram_size = 0x50000,              // "SRAM" byte size in hex from DS Fig 18
+            .bootrom_base = 0x00100000,        // "System memory" starting address from DS Fig 18
+            .bootrom_size = 0xEDC0             // "System memory" byte size in hex from DS Fig 18
+        },
         { // table 2, PM0063
             .chip_id = STM32_CHIPID_F1_MEDIUM,
             .description = "F1 Medium-density device",
@@ -210,6 +225,15 @@ extern "C" {
             .bootrom_base = 0x1fff0000,
             .bootrom_size = 0x7800
         },
+        {
+            .chip_id = STM32_CHIPID_F4_DSI,
+            .description = "F46x and F47x device",
+            .flash_size_reg = 0x1FFF7A22,  /* As in rm0090 since Rev 2*/
+            .flash_pagesize = 0x4000,
+            .sram_size = 0x40000,
+            .bootrom_base = 0x1fff0000,
+            .bootrom_size = 0x7800
+        },
         {
             .chip_id = STM32_CHIPID_F4_HD,
             .description = "F42x and F43x device",