// Max data transfer size.
// 6kB = max mem32_read block, 8kB sram
//#define Q_BUF_LEN 96
-#define Q_BUF_LEN 1024 * 100
+#define Q_BUF_LEN (1024 * 100)
// st-link vendor cmd's
#define USB_ST_VID 0x0483
// cortex m3 technical reference manual
#define CM3_REG_CPUID 0xE000ED00
+#define CM3_REG_FP_CTRL 0xE0002000
+#define CM3_REG_FP_COMP0 0xE0002008
+
+/* Enough space to hold both a V2 command or a V1 command packaged as generic scsi*/
+#define C_BUF_LEN 32
typedef struct {
uint32_t r[16];
struct _stlink_backend *backend;
void *backend_data;
+ // Room for the command header
+ unsigned char c_buf[C_BUF_LEN];
// Data transferred from or to device
unsigned char q_buf[Q_BUF_LEN];
int q_len;
/* sram settings */
#define STM32_SRAM_BASE 0x20000000
#define STM32_SRAM_SIZE (8 * 1024)
+#define STM32L_SRAM_SIZE (16 * 1024)
stm32_addr_t sram_base;
size_t sram_size;
// unprocessed
int stlink_erase_flash_mass(stlink_t* sl);
int stlink_write_flash(stlink_t* sl, stm32_addr_t address, uint8_t* data, unsigned length);
+ int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr);
// PUBLIC
uint16_t stlink_chip_id(stlink_t *sl);