#define STLINK_DEBUG_WRITEDEBUGREG 0x0f
#define STLINK_DEBUG_ENTER_SWD 0xa3
#define STLINK_DEBUG_ENTER_JTAG 0x00
+#define STLINK_DEBUG_HARDRESET 0x3c
// TODO - possible poor names...
#define STLINK_SWD_ENTER 0x30
#define STM32_CHIPID_F1_LOW 0x412
#define STM32_CHIPID_F4 0x413
#define STM32_CHIPID_F1_HIGH 0x414
-
+#define STM32_CHIPID_L4 0x415 /* Seen on L4x6 (RM0351) */
#define STM32_CHIPID_L1_MEDIUM 0x416
#define STM32_CHIPID_L0 0x417
#define STM32_CHIPID_F1_CONN 0x418
#define STM32_CHIPID_F4_HD 0x419
#define STM32_CHIPID_F1_VL_MEDIUM_LOW 0x420
+#define STM32_CHIPID_F446 0x421
#define STM32_CHIPID_F3 0x422
#define STM32_CHIPID_F4_LP 0x423
#define STM32_CHIPID_L1_MEDIUM_PLUS 0x427
#define STM32_CHIPID_F1_VL_HIGH 0x428
+#define STM32_CHIPID_L1_CAT2 0x429
#define STM32_CHIPID_F1_XL 0x430
#define STM32_CHIPID_F3_SMALL 0x439
#define STM32_CHIPID_F0 0x440
-
+#define STM32_CHIPID_F09X 0x442
#define STM32_CHIPID_F0_SMALL 0x444
#define STM32_CHIPID_F04 0x445
+#define STM32_CHIPID_F303_HIGH 0x446
+
#define STM32_CHIPID_F0_CAN 0x448
+#define STM32_CHIPID_F7 0x449
+
/*
* 0x436 is actually assigned to some L1 chips that are called "Medium-Plus"
* and some that are called "High". 0x427 is assigned to the other "Medium-
// These maps are from a combination of the Programming Manuals, and
// also the Reference manuals. (flash size reg is normally in ref man)
static const chip_params_t devices[] = {
+ {
+ //RM0385 and DS10916 document was used to find these paramaters
+ .chip_id = STM32_CHIPID_F7,
+ .description = "F7 device",
+ .flash_size_reg = 0x1ff0f442, // section 41.2
+ .flash_pagesize = 0x800, // No flash pages
+ .sram_size = 0x50000, // "SRAM" byte size in hex from DS Fig 18
+ .bootrom_base = 0x00100000, // "System memory" starting address from DS Fig 18
+ .bootrom_size = 0xEDC0 // "System memory" byte size in hex from DS Fig 18
+ },
{ // table 2, PM0063
.chip_id = STM32_CHIPID_F1_MEDIUM,
.description = "F1 Medium-density device",
.bootrom_base = 0x1ff00000,
.bootrom_size = 0x1000
},
+ {
+ .chip_id = STM32_CHIPID_L1_CAT2,
+ .description = "L1 Cat.2 device",
+ .flash_size_reg = 0x1ff8004c,
+ .flash_pagesize = 0x100,
+ .sram_size = 0x8000,
+ .bootrom_base = 0x1ff00000,
+ .bootrom_size = 0x1000
+ },
{
.chip_id = STM32_CHIPID_L1_MEDIUM_PLUS,
.description = "L1 Medium-Plus-density device",
.bootrom_base = 0x1ffff000,
.bootrom_size = 0x800
},
+ {
+ // STM32F446x family. Support based on DM00135183.pdf (RM0390) document.
+ .chip_id = STM32_CHIPID_F446,
+ .description = "F446 device",
+ .flash_size_reg = 0x1fff7a22,
+ .flash_pagesize = 0x20000,
+ .sram_size = 0x20000,
+ .bootrom_base = 0x1fff0000,
+ .bootrom_size = 0x7800
+ },
{
// This is STK32F303VCT6 device from STM32 F3 Discovery board.
// Support based on DM00043574.pdf (RM0316) document.
.bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2
.bootrom_size = 0xC00 // "System memory" byte size in hex from Table 2
},
+ {
+ .chip_id = STM32_CHIPID_F09X,
+ .description = "F09X device",
+ .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735)
+ .flash_pagesize = 0x800, // Page sizes listed in Table 4 (pg 56)
+ .sram_size = 0x8000, // "SRAM" byte size in hex from Table 2 (pg 50)
+ .bootrom_base = 0x1fffd800, // "System memory" starting address from Table 2
+ .bootrom_size = 0x2000 // "System memory" byte size in hex from Table 2
+ },
{
//Use this as an example for mapping future chips:
//RM0091 document was used to find these paramaters
.description = "F04x device",
.flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735)
.flash_pagesize = 0x400, // Page sizes listed in Table 4
- .sram_size = 0x1000, // "SRAM" byte size in hex from Table 2
+ .sram_size = 0x1800, // "SRAM" byte size in hex from Table 2
.bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2
.bootrom_size = 0xC00 // "System memory" byte size in hex from Table 2
},
.bootrom_base = 0x1fffd800,
.bootrom_size = 0x2000
},
+ {
+ // This is STK32F303RET6 device from STM32 F3 Nucelo board.
+ // Support based on DM00043574.pdf (RM0316) document rev 5.
+ .chip_id = STM32_CHIPID_F303_HIGH,
+ .description = "F303 high density device",
+ .flash_size_reg = 0x1ffff7cc, // 34.2.1 Flash size data register
+ .flash_pagesize = 0x800, // 4.2.1 Flash memory organization
+ .sram_size = 0x10000, // 3.3 Embedded SRAM
+ .bootrom_base = 0x1fffd800, // 3.3.2 / Table 4 System Memory
+ .bootrom_size = 0x2000
+ },
+ {
+ // STM32L4x6
+ // From RM0351.
+ .chip_id = STM32_CHIPID_L4,
+ .description = "L4 device",
+ .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 45.2, page 1671)
+ .flash_pagesize = 0x800, // 2K (sec 3.2, page 78; also appears in sec 3.3.1 and tables 4-6 on pages 79-81)
+ // SRAM1 is "up to" 96k in the standard Cortex-M memory map;
+ // SRAM2 is 32k mapped at at 0x10000000 (sec 2.3, page 73 for
+ // sizes; table 2, page 74 for SRAM2 location)
+ .sram_size = 0x18000,
+ .bootrom_base = 0x1fff0000, // Tables 4-6, pages 80-81 (Bank 1 system memory)
+ .bootrom_size = 0x7000 // 28k (per bank), same source as base
+ },
};
projects / fw / stlink / blobdiff