Support for STM32L1 medium-plus chips with chip id 0x427

[fw/stlink] / src / stlink-common.h

diff --git a/src/stlink-common.h b/src/stlink-common.h
index f0141aa0634bdf8c68a22218fc6313ec7e7a4768..7553224cd9ba4007c8a76a41d92618413c32d256 100644 (file)
--- a/src/stlink-common.h
+++ b/src/stlink-common.h
@@ -104,13 +104,20 @@ extern "C" {
 #define STM32_CHIPID_F4 0x413
 #define STM32_CHIPID_F1_HIGH 0x414
 #define STM32_CHIPID_L1_MEDIUM 0x416
-#define STM32_CHIPID_L1_MEDIUM_PLUS 0x436
+#define STM32_CHIPID_L1_MEDIUM_PLUS 0x427
+/*
+ * 0x436 is actually assigned to some L1 chips that are called "Medium-Plus"
+ * and some that are called "High".  0x427 is assigned to the other "Medium-
+ * plus" chips.  To make it a bit simpler we just call 427 MEDIUM_PLUS and
+ * 0x436 HIGH.
+ */
 #define STM32_CHIPID_L1_HIGH 0x436
 #define STM32_CHIPID_F1_CONN 0x418
 #define STM32_CHIPID_F1_VL_MEDIUM 0x420
 #define STM32_CHIPID_F1_VL_HIGH 0x428
 #define STM32_CHIPID_F1_XL 0x430
 #define STM32_CHIPID_F0 0x440
+#define STM32_CHIPID_F0_SMALL 0x444
 
 // Constant STM32 memory map figures
 #define STM32_FLASH_BASE 0x08000000
@@ -140,7 +147,7 @@ extern "C" {
 // also the Reference manuals.  (flash size reg is normally in ref man)
 static const chip_params_t devices[] = {
         { // table 2, PM0063
-            .chip_id = 0x410,
+            .chip_id = STM32_CHIPID_F1_MEDIUM,
             .description = "F1 Medium-density device",
             .flash_size_reg = 0x1ffff7e0,
                     .flash_pagesize = 0x400,
@@ -149,7 +156,7 @@ static const chip_params_t devices[] = {
                     .bootrom_size = 0x800
         },
         {  // table 1, PM0059
-            .chip_id = 0x411,
+            .chip_id = STM32_CHIPID_F2,
                     .description = "F2 device",
                     .flash_size_reg = 0, /* no flash size reg found in the docs! */
                     .flash_pagesize = 0x20000,
@@ -158,7 +165,7 @@ static const chip_params_t devices[] = {
                     .bootrom_size = 0x7800
         },
         { // PM0063
-            .chip_id = 0x412,
+            .chip_id = STM32_CHIPID_F1_LOW,
                     .description = "F1 Low-density device",
                     .flash_size_reg = 0x1ffff7e0,
                     .flash_pagesize = 0x400,
@@ -167,7 +174,7 @@ static const chip_params_t devices[] = {
                     .bootrom_size = 0x800
         },
         {
-            .chip_id = 0x413,
+            .chip_id = STM32_CHIPID_F4,
                     .description = "F4 device",
                     .flash_size_reg = 0x1FFF7A10,  //RM0090 error same as unique ID
                     .flash_pagesize = 0x4000,
@@ -176,7 +183,7 @@ static const chip_params_t devices[] = {
                     .bootrom_size = 0x7800
         },
         {
-            .chip_id = 0x414,
+            .chip_id = STM32_CHIPID_F1_HIGH,
                     .description = "F1 High-density device",
                     .flash_size_reg = 0x1ffff7e0,
                     .flash_pagesize = 0x800,
@@ -187,7 +194,7 @@ static const chip_params_t devices[] = {
         {
           // This ignores the EEPROM! (and uses the page erase size,
           // not the sector write protection...)
-            .chip_id = 0x416,
+            .chip_id = STM32_CHIPID_L1_MEDIUM,
                     .description = "L1 Med-density device",
                     .flash_size_reg = 0x1ff8004c,
                     .flash_pagesize = 0x100,
@@ -198,14 +205,24 @@ static const chip_params_t devices[] = {
         {
             .chip_id = STM32_CHIPID_L1_MEDIUM_PLUS,
                     .description = "L1 Medium-Plus-density device",
-                    .flash_size_reg = 0x1ff800CC,
+                    .flash_size_reg = 0x1ff800cc,
                     .flash_pagesize = 0x100,
-                    .sram_size = 0x8000,
+                    .sram_size = 0x8000,/*Not completely clear if there are some with 48K*/
                     .bootrom_base = 0x1ff00000,
                     .bootrom_size = 0x1000
         },
         {
-            .chip_id = 0x418,
+            .chip_id = STM32_CHIPID_L1_HIGH,
+                    .description = "L1 High-density device",
+                    .flash_size_reg = 0x1ff800cc,
+                    .flash_pagesize = 0x100,
+                    .sram_size = 0xC000, /*Not completely clear if there are some with 32K*/
+                    .bootrom_base = 0x1ff00000,
+                    .bootrom_size = 0x1000
+        },
+
+        {
+            .chip_id = STM32_CHIPID_F1_CONN,
                     .description = "F1 Connectivity line device",
                     .flash_size_reg = 0x1ffff7e0,
                     .flash_pagesize = 0x800,
@@ -214,7 +231,7 @@ static const chip_params_t devices[] = {
                     .bootrom_size = 0x4800
         },
         {
-            .chip_id = 0x420,
+            .chip_id = STM32_CHIPID_F1_VL_MEDIUM,
                     .description = "F1 Medium-density Value Line device",
                     .flash_size_reg = 0x1ffff7e0,
                     .flash_pagesize = 0x400,
@@ -225,7 +242,7 @@ static const chip_params_t devices[] = {
         {
            // This is STK32F303VCT6 device from STM32 F3 Discovery board.
            // Support based on DM00043574.pdf (RM0316) document.
-            .chip_id = 0x422,
+            .chip_id = STM32_CHIPID_F3,
                     .description = "F3 device",
                     .flash_size_reg = 0x1ffff7cc,
                     .flash_pagesize = 0x800,
@@ -236,7 +253,7 @@ static const chip_params_t devices[] = {
         {
            // This is STK32F373VCT6 device from STM32 F373 eval board
            // Support based on 303 above (37x and 30x have same memory map)
-            .chip_id = 0x432,
+            .chip_id = STM32_CHIPID_F37x,
                     .description = "F3 device",
                     .flash_size_reg = 0x1ffff7cc,
                     .flash_pagesize = 0x800,
@@ -245,7 +262,7 @@ static const chip_params_t devices[] = {
                     .bootrom_size = 0x800
         },
         {
-            .chip_id = 0x428,
+            .chip_id = STM32_CHIPID_F1_VL_HIGH,
                     .description = "F1 High-density value line device",
                     .flash_size_reg = 0x1ffff7e0,
                     .flash_pagesize = 0x800,
@@ -254,7 +271,7 @@ static const chip_params_t devices[] = {
                     .bootrom_size = 0x800
         },
         {
-            .chip_id = 0x430,
+            .chip_id = STM32_CHIPID_F1_XL,
                     .description = "F1 XL-density device",
                     .flash_size_reg = 0x1ffff7e0,
                     .flash_pagesize = 0x800,
@@ -265,14 +282,25 @@ static const chip_params_t devices[] = {
         {
             //Use this as an example for mapping future chips:
             //RM0091 document was used to find these paramaters
-            .chip_id = 0x440,
+            .chip_id = STM32_CHIPID_F0,
                     .description = "F0 device",
                     .flash_size_reg = 0x1ffff7cc,      // "Flash size data register" (pg735)
                     .flash_pagesize = 0x400,           // Page sizes listed in Table 4
                     .sram_size = 0x2000,               // "SRAM" byte size in hex from Table 2
                     .bootrom_base = 0x1fffec00,                // "System memory" starting address from Table 2
                     .bootrom_size = 0xC00              // "System memory" byte size in hex from Table 2
-        }
+        },
+        {
+            //Use this as an example for mapping future chips:
+            //RM0091 document was used to find these paramaters
+            .chip_id = STM32_CHIPID_F0_SMALL,
+                    .description = "F0 small device",
+                    .flash_size_reg = 0x1ffff7cc,      // "Flash size data register" (pg735)
+                    .flash_pagesize = 0x400,           // Page sizes listed in Table 4
+                    .sram_size = 0x1000,               // "SRAM" byte size in hex from Table 2
+                    .bootrom_base = 0x1fffec00,                // "System memory" starting address from Table 2
+                    .bootrom_size = 0xC00              // "System memory" byte size in hex from Table 2
+        },
  };