Merge branch 'master' of git://github.com/texane/stlink

[fw/stlink] / src / stlink-common.h

diff --git a/src/stlink-common.h b/src/stlink-common.h
index a9834a476ca10b51b1ee4e98735850035ebf7e4f..6fcb2194e10cc35fc9b63fcf1718983376ed4260 100644 (file)
--- a/src/stlink-common.h
+++ b/src/stlink-common.h
@@ -81,10 +81,18 @@ extern "C" {
 #define CM3_REG_FP_COMP0 0xE0002008
 
 /* cortex core ids */
+    // TODO clean this up...
 #define STM32VL_CORE_ID 0x1ba01477
 #define STM32L_CORE_ID 0x2ba01477
 #define STM32F4_CORE_ID 0x2ba01477
-    
+#define CORE_M3_R1 0x1BA00477
+#define CORE_M3_R2 0x4BA00477
+#define CORE_M4_R0 0x2BA01477
+
+/*
+ * Chip IDs are explained in the appropriate programming manual for the
+ * DBGMCU_IDCODE register (0xE0042000)
+ */
 // stm32 chipids, only lower 12 bits..
 #define STM32_CHIPID_F1_MEDIUM 0x410
 #define STM32_CHIPID_F2 0x411
@@ -101,16 +109,10 @@ extern "C" {
 #define STM32_FLASH_BASE 0x08000000
 #define STM32_SRAM_BASE 0x20000000
 
-/*
- * Chip IDs are explained in the appropriate programming manual for the
- * DBGMCU_IDCODE register (0xE0042000)
- */
-#define CORE_M3_R1 0x1BA00477
-#define CORE_M3_R2 0x4BA00477
-#define CORE_M4_R0 0x2BA01477
-
-/* using chip id for F4 ident, since core id is same as F1 */
-#define STM32F4_CHIP_ID 0x413
+/* Cortex™-M3 Technical Reference Manual */
+/* Debug Halting Control and Status Register */
+#define DHCSR 0xe000edf0
+#define DBGKEY 0xa05f0000
 
 /* Enough space to hold both a V2 command or a V1 command packaged as generic scsi*/
 #define C_BUF_LEN 32
@@ -358,6 +360,7 @@ extern "C" {
     int stlink_erase_flash_mass(stlink_t* sl);
     int stlink_write_flash(stlink_t* sl, stm32_addr_t address, uint8_t* data, unsigned length);
     int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr);
+    int stlink_fwrite_sram(stlink_t *sl, const char* path, stm32_addr_t addr);
     int stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, unsigned length);
     
     // PUBLIC