#define STM32_CHIPID_F37x 0x432
#define STM32_CHIPID_F4_DE 0x433
+#define STM32_CHIPID_F4_DE 0x433
+
+#define STM32_CHIPID_F4_DSI 0x434
#define STM32_CHIPID_L1_HIGH 0x436
#define STM32_CHIPID_L152_RE 0x437
#define STM32_CHIPID_F0_CAN 0x448
+#define STM32_CHIPID_F7 0x449
+
/*
* 0x436 is actually assigned to some L1 chips that are called "Medium-Plus"
* and some that are called "High". 0x427 is assigned to the other "Medium-
// These maps are from a combination of the Programming Manuals, and
// also the Reference manuals. (flash size reg is normally in ref man)
static const chip_params_t devices[] = {
+ {
+ //RM0385 and DS10916 document was used to find these paramaters
+ .chip_id = STM32_CHIPID_F7,
+ .description = "F7 device",
+ .flash_size_reg = 0x1ff0f442, // section 41.2
+ .flash_pagesize = 0x800, // No flash pages
+ .sram_size = 0x50000, // "SRAM" byte size in hex from DS Fig 18
+ .bootrom_base = 0x00100000, // "System memory" starting address from DS Fig 18
+ .bootrom_size = 0xEDC0 // "System memory" byte size in hex from DS Fig 18
+ },
{ // table 2, PM0063
.chip_id = STM32_CHIPID_F1_MEDIUM,
.description = "F1 Medium-density device",
.bootrom_base = 0x1fff0000,
.bootrom_size = 0x7800
},
+ {
+ .chip_id = STM32_CHIPID_F4_DSI,
+ .description = "F46x and F47x device",
+ .flash_size_reg = 0x1FFF7A22, /* As in rm0090 since Rev 2*/
+ .flash_pagesize = 0x4000,
+ .sram_size = 0x40000,
+ .bootrom_base = 0x1fff0000,
+ .bootrom_size = 0x7800
+ },
{
.chip_id = STM32_CHIPID_F4_HD,
.description = "F42x and F43x device",
typedef struct _stlink_backend {
void (*close) (stlink_t * sl);
- void (*exit_debug_mode) (stlink_t * sl);
- void (*enter_swd_mode) (stlink_t * sl);
- void (*enter_jtag_mode) (stlink_t * stl);
- void (*exit_dfu_mode) (stlink_t * stl);
- void (*core_id) (stlink_t * stl);
- void (*reset) (stlink_t * stl);
- void (*jtag_reset) (stlink_t * stl, int value);
- void (*run) (stlink_t * stl);
- void (*status) (stlink_t * stl);
- void (*version) (stlink_t *sl);
- uint32_t (*read_debug32) (stlink_t *sl, uint32_t addr);
- void (*read_mem32) (stlink_t *sl, uint32_t addr, uint16_t len);
- void (*write_debug32) (stlink_t *sl, uint32_t addr, uint32_t data);
- void (*write_mem32) (stlink_t *sl, uint32_t addr, uint16_t len);
- void (*write_mem8) (stlink_t *sl, uint32_t addr, uint16_t len);
- void (*read_all_regs) (stlink_t *sl, reg * regp);
- void (*read_reg) (stlink_t *sl, int r_idx, reg * regp);
- void (*read_all_unsupported_regs) (stlink_t *sl, reg *regp);
- void (*read_unsupported_reg) (stlink_t *sl, int r_idx, reg *regp);
- void (*write_unsupported_reg) (stlink_t *sl, uint32_t value, int idx, reg *regp);
- void (*write_reg) (stlink_t *sl, uint32_t reg, int idx);
- void (*step) (stlink_t * stl);
+ int (*exit_debug_mode) (stlink_t * sl);
+ int (*enter_swd_mode) (stlink_t * sl);
+ int (*enter_jtag_mode) (stlink_t * stl);
+ int (*exit_dfu_mode) (stlink_t * stl);
+ int (*core_id) (stlink_t * stl);
+ int (*reset) (stlink_t * stl);
+ int (*jtag_reset) (stlink_t * stl, int value);
+ int (*run) (stlink_t * stl);
+ int (*status) (stlink_t * stl);
+ int (*version) (stlink_t *sl);
+ int (*read_debug32) (stlink_t *sl, uint32_t addr, uint32_t *data);
+ int (*read_mem32) (stlink_t *sl, uint32_t addr, uint16_t len);
+ int (*write_debug32) (stlink_t *sl, uint32_t addr, uint32_t data);
+ int (*write_mem32) (stlink_t *sl, uint32_t addr, uint16_t len);
+ int (*write_mem8) (stlink_t *sl, uint32_t addr, uint16_t len);
+ int (*read_all_regs) (stlink_t *sl, reg * regp);
+ int (*read_reg) (stlink_t *sl, int r_idx, reg * regp);
+ int (*read_all_unsupported_regs) (stlink_t *sl, reg *regp);
+ int (*read_unsupported_reg) (stlink_t *sl, int r_idx, reg *regp);
+ int (*write_unsupported_reg) (stlink_t *sl, uint32_t value, int idx, reg *regp);
+ int (*write_reg) (stlink_t *sl, uint32_t reg, int idx);
+ int (*step) (stlink_t * stl);
int (*current_mode) (stlink_t * stl);
- void (*force_debug) (stlink_t *sl);
+ int (*force_debug) (stlink_t *sl);
int32_t (*target_voltage) (stlink_t *sl);
} stlink_backend_t;
void stlink_exit_debug_mode(stlink_t *sl);
void stlink_exit_dfu_mode(stlink_t *sl);
void stlink_close(stlink_t *sl);
- uint32_t stlink_core_id(stlink_t *sl);
+ void stlink_core_id(stlink_t *sl);
void stlink_reset(stlink_t *sl);
void stlink_jtag_reset(stlink_t *sl, int value);
void stlink_run(stlink_t *sl);
void stlink_status(stlink_t *sl);
void stlink_version(stlink_t *sl);
- uint32_t stlink_read_debug32(stlink_t *sl, uint32_t addr);
+ void stlink_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data);
void stlink_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len);
void stlink_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data);
void stlink_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len);
// unprocessed
int stlink_erase_flash_mass(stlink_t* sl);
- int stlink_write_flash(stlink_t* sl, stm32_addr_t address, uint8_t* data, uint32_t length);
+ int stlink_write_flash(stlink_t* sl, stm32_addr_t address, uint8_t* data, uint32_t length, uint8_t eraseonly);
int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr);
int stlink_fwrite_sram(stlink_t *sl, const char* path, stm32_addr_t addr);
int stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, uint32_t length);