Remove -sg's private version decoding

[fw/stlink] / src / stlink-common.h

diff --git a/src/stlink-common.h b/src/stlink-common.h
index b357c7a52a533438aa68f61b2a4d2ab1a049295d..2ac56f2b642c4972778d601be0c089c0647dd493 100644 (file)
--- a/src/stlink-common.h
+++ b/src/stlink-common.h
@@ -18,7 +18,7 @@ extern "C" {
     // Max data transfer size.
     // 6kB = max mem32_read block, 8kB sram
     //#define Q_BUF_LEN        96
-#define Q_BUF_LEN      1024 * 100
+#define Q_BUF_LEN                      (1024 * 100)
 
     // st-link vendor cmd's
 #define USB_ST_VID                     0x0483
@@ -73,6 +73,11 @@ extern "C" {
 
 // cortex m3 technical reference manual
 #define CM3_REG_CPUID 0xE000ED00
+#define CM3_REG_FP_CTRL 0xE0002000
+#define CM3_REG_FP_COMP0 0xE0002008
+
+/* Enough space to hold both a V2 command or a V1 command packaged as generic scsi*/
+#define C_BUF_LEN 32
 
     typedef struct {
         uint32_t r[16];
@@ -140,6 +145,8 @@ extern "C" {
         struct _stlink_backend *backend;
         void *backend_data;
 
+        // Room for the command header
+        unsigned char c_buf[C_BUF_LEN];
         // Data transferred from or to device
         unsigned char q_buf[Q_BUF_LEN];
         int q_len;
@@ -168,9 +175,11 @@ extern "C" {
         /* sram settings */
 #define STM32_SRAM_BASE 0x20000000
 #define STM32_SRAM_SIZE (8 * 1024)
+#define STM32L_SRAM_SIZE (16 * 1024)
         stm32_addr_t sram_base;
         size_t sram_size;
 
+        struct stlink_version_ version;
     };
 
     // some quick and dirty logging...
@@ -204,6 +213,7 @@ extern "C" {
     // unprocessed
     int stlink_erase_flash_mass(stlink_t* sl);
     int stlink_write_flash(stlink_t* sl, stm32_addr_t address, uint8_t* data, unsigned length);
+    int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr);
     
     // PUBLIC
     uint16_t stlink_chip_id(stlink_t *sl);