Fix getting error message when successfully using stlinkV2
[fw/stlink] / src / stlink-common.h
index 532f7d928de61a12aee1a2e5cf69edd6adbdea1e..04a1081017806e3601e8a79ac38e4d519ab6d31c 100644 (file)
@@ -108,7 +108,7 @@ extern "C" {
 #define STM32_CHIPID_L0             0x417
 #define STM32_CHIPID_F1_CONN        0x418
 #define STM32_CHIPID_F4_HD          0x419
-#define STM32_CHIPID_F1_VL_MEDIUM   0x420
+#define STM32_CHIPID_F1_VL_MEDIUM_LOW 0x420
 
 #define STM32_CHIPID_F3             0x422
 #define STM32_CHIPID_F4_LP          0x423
@@ -125,13 +125,15 @@ extern "C" {
 
 #define STM32_CHIPID_L1_HIGH        0x436
 #define STM32_CHIPID_L152_RE        0x437
-
+#define STM32_CHIPID_F334           0x438
 
 #define STM32_CHIPID_F3_SMALL       0x439
 #define STM32_CHIPID_F0             0x440
-
+#define STM32_CHIPID_F09X           0x442
 #define STM32_CHIPID_F0_SMALL       0x444
 
+#define STM32_CHIPID_F04            0x445
+
 #define STM32_CHIPID_F0_CAN         0x448
 
     /*
@@ -209,7 +211,7 @@ extern "C" {
             .description = "F42x and F43x device",
             .flash_size_reg = 0x1FFF7A22,  /* As in rm0090 since Rev 2*/
             .flash_pagesize = 0x4000,
-            .sram_size = 0x30000,
+            .sram_size = 0x40000,
             .bootrom_base = 0x1fff0000,
             .bootrom_size = 0x7800
         },
@@ -296,12 +298,12 @@ extern "C" {
             .bootrom_base = 0x1fffb000,
             .bootrom_size = 0x4800
         },
-        {
-            .chip_id = STM32_CHIPID_F1_VL_MEDIUM,
-            .description = "F1 Medium-density Value Line device",
+        {//Low and Medium density VL have same chipid. RM0041 25.6.1
+            .chip_id = STM32_CHIPID_F1_VL_MEDIUM_LOW,
+            .description = "F1 Medium/Low-density Value Line device",
             .flash_size_reg = 0x1ffff7e0,
             .flash_pagesize = 0x400,
-            .sram_size = 0x2000,
+            .sram_size = 0x2000,//0x1000 for low density devices
             .bootrom_base = 0x1ffff000,
             .bootrom_size = 0x800
         },
@@ -367,6 +369,26 @@ extern "C" {
             .bootrom_base = 0x1fffec00,                // "System memory" starting address from Table 2
             .bootrom_size = 0xC00              // "System memory" byte size in hex from Table 2
         },
+       {
+            .chip_id = STM32_CHIPID_F09X,
+            .description = "F09X device",
+            .flash_size_reg = 0x1ffff7cc,      // "Flash size data register" (pg735)
+            .flash_pagesize = 0x800,           // Page sizes listed in Table 4 (pg 56)
+            .sram_size = 0x8000,               // "SRAM" byte size in hex from Table 2 (pg 50)
+            .bootrom_base = 0x1fffd800,                // "System memory" starting address from Table 2
+            .bootrom_size = 0x2000             // "System memory" byte size in hex from Table 2
+        },
+        {
+            //Use this as an example for mapping future chips:
+            //RM0091 document was used to find these paramaters
+            .chip_id = STM32_CHIPID_F04,
+            .description = "F04x device",
+            .flash_size_reg = 0x1ffff7cc,      // "Flash size data register" (pg735)
+            .flash_pagesize = 0x400,           // Page sizes listed in Table 4
+            .sram_size = 0x1000,               // "SRAM" byte size in hex from Table 2
+            .bootrom_base = 0x1fffec00,                // "System memory" starting address from Table 2
+            .bootrom_size = 0xC00              // "System memory" byte size in hex from Table 2
+        },
         {
             //Use this as an example for mapping future chips:
             //RM0091 document was used to find these paramaters
@@ -399,6 +421,18 @@ extern "C" {
             .bootrom_base = 0x1ff0000,
             .bootrom_size = 0x1000
         },
+        {
+            // STM32F334
+            // RM0364 document was used to find these parameters
+            .chip_id = STM32_CHIPID_F334,
+            .description = "F334 device",
+            .flash_size_reg = 0x1ffff7cc,
+            .flash_pagesize = 0x800,
+            .sram_size = 0x3000,
+            .bootrom_base = 0x1fffd800,
+            .bootrom_size = 0x2000
+        },
+
  };