}
+/* todo: stm32l15xxx flash memory, pm0062 manual */
-/* FPEC flash controller interface, pm0063 manual
- */
+/* stm32f FPEC flash controller interface, pm0063 manual */
#define FLASH_REGS_ADDR 0x40022000
#define FLASH_REGS_SIZE 0x28
#define FLASH_CR_STRT 6
#define FLASH_CR_LOCK 7
+
+//32L = 32F1 same CoreID as 32F4!
+#define STM32L_FLASH_REGS_ADDR ((uint32_t)0x40023c00)
+#define STM32L_FLASH_ACR (STM32L_FLASH_REGS_ADDR + 0x00)
+#define STM32L_FLASH_PECR (STM32L_FLASH_REGS_ADDR + 0x04)
+#define STM32L_FLASH_PDKEYR (STM32L_FLASH_REGS_ADDR + 0x08)
+#define STM32L_FLASH_PEKEYR (STM32L_FLASH_REGS_ADDR + 0x0c)
+#define STM32L_FLASH_PRGKEYR (STM32L_FLASH_REGS_ADDR + 0x10)
+#define STM32L_FLASH_OPTKEYR (STM32L_FLASH_REGS_ADDR + 0x14)
+#define STM32L_FLASH_SR (STM32L_FLASH_REGS_ADDR + 0x18)
+#define STM32L_FLASH_OBR (STM32L_FLASH_REGS_ADDR + 0x0c)
+#define STM32L_FLASH_WRPR (STM32L_FLASH_REGS_ADDR + 0x20)
+
+
+//STM32F4
+#define FLASH_F4_REGS_ADDR ((uint32_t)0x40023c00)
+#define FLASH_F4_KEYR (FLASH_F4_REGS_ADDR + 0x04)
+#define FLASH_F4_OPT_KEYR (FLASH_F4_REGS_ADDR + 0x08)
+#define FLASH_F4_SR (FLASH_F4_REGS_ADDR + 0x0c)
+#define FLASH_F4_CR (FLASH_F4_REGS_ADDR + 0x10)
+#define FLASH_F4_OPT_CR (FLASH_F4_REGS_ADDR + 0x14)
+#define FLASH_F4_CR_STRT 16
+#define FLASH_F4_CR_LOCK 31
+#define FLASH_F4_CR_SER 1
+#define FLASH_F4_CR_SNB 3
+#define FLASH_F4_CR_SNB_MASK 0x38
+#define FLASH_F4_SR_BSY 16
+
+
void write_uint32(unsigned char* buf, uint32_t ui) {
if (!is_bigendian()) { // le -> le (don't swap)
buf[0] = ((unsigned char*) &ui)[0];
char *p = (char *) &ui;
if (!is_bigendian()) { // le -> le (don't swap)
- p[0] = c[pt];
+ p[0] = c[pt + 0];
p[1] = c[pt + 1];
p[2] = c[pt + 2];
p[3] = c[pt + 3];
p[0] = c[pt + 3];
p[1] = c[pt + 2];
p[2] = c[pt + 1];
- p[3] = c[pt];
+ p[3] = c[pt + 0];
}
return ui;
}
}
static inline uint32_t read_flash_cr(stlink_t *sl) {
- stlink_read_mem32(sl, FLASH_CR, sizeof (uint32_t));
+ if(sl->chip_id==STM32F4_CHIP_ID)
+ stlink_read_mem32(sl, FLASH_F4_CR, sizeof (uint32_t));
+ else
+ stlink_read_mem32(sl, FLASH_CR, sizeof (uint32_t));
+ fprintf(stdout, "CR:%X\n", *(uint32_t*) sl->q_buf);
return *(uint32_t*) sl->q_buf;
}
static inline unsigned int is_flash_locked(stlink_t *sl) {
/* return non zero for true */
- return read_flash_cr(sl) & (1 << FLASH_CR_LOCK);
+ if(sl->chip_id==STM32F4_CHIP_ID)
+ return read_flash_cr(sl) & (1 << FLASH_F4_CR_LOCK);
+ else
+ return read_flash_cr(sl) & (1 << FLASH_CR_LOCK);
}
static void unlock_flash(stlink_t *sl) {
an invalid sequence results in a definitive lock of
the FPEC block until next reset.
*/
+ if(sl->chip_id==STM32F4_CHIP_ID) {
+ write_uint32(sl->q_buf, FLASH_KEY1);
+ stlink_write_mem32(sl, FLASH_F4_KEYR, sizeof (uint32_t));
+ write_uint32(sl->q_buf, FLASH_KEY2);
+ stlink_write_mem32(sl, FLASH_F4_KEYR, sizeof (uint32_t));
+ }
+ else {
+ write_uint32(sl->q_buf, FLASH_KEY1);
+ stlink_write_mem32(sl, FLASH_KEYR, sizeof (uint32_t));
+ write_uint32(sl->q_buf, FLASH_KEY2);
+ stlink_write_mem32(sl, FLASH_KEYR, sizeof (uint32_t));
+ }
- write_uint32(sl->q_buf, FLASH_KEY1);
- stlink_write_mem32(sl, FLASH_KEYR, sizeof (uint32_t));
-
- write_uint32(sl->q_buf, FLASH_KEY2);
- stlink_write_mem32(sl, FLASH_KEYR, sizeof (uint32_t));
}
static int unlock_flash_if(stlink_t *sl) {
}
static void lock_flash(stlink_t *sl) {
- /* write to 1 only. reset by hw at unlock sequence */
-
- const uint32_t n = read_flash_cr(sl) | (1 << FLASH_CR_LOCK);
-
- write_uint32(sl->q_buf, n);
- stlink_write_mem32(sl, FLASH_CR, sizeof (uint32_t));
+ if(sl->chip_id==STM32F4_CHIP_ID) {
+ const uint32_t n = read_flash_cr(sl) | (1 << FLASH_F4_CR_LOCK);
+ write_uint32(sl->q_buf, n);
+ stlink_write_mem32(sl, FLASH_F4_CR, sizeof (uint32_t));
+ }
+ else {
+ /* write to 1 only. reset by hw at unlock sequence */
+ const uint32_t n = read_flash_cr(sl) | (1 << FLASH_CR_LOCK);
+ write_uint32(sl->q_buf, n);
+ stlink_write_mem32(sl, FLASH_CR, sizeof (uint32_t));
+ }
}
+
static void set_flash_cr_pg(stlink_t *sl) {
- const uint32_t n = 1 << FLASH_CR_PG;
- write_uint32(sl->q_buf, n);
- stlink_write_mem32(sl, FLASH_CR, sizeof (uint32_t));
+ if(sl->chip_id==STM32F4_CHIP_ID) {
+ uint32_t x = read_flash_cr(sl);
+ x |= (1 << FLASH_CR_PG);
+ write_uint32(sl->q_buf, x);
+ stlink_write_mem32(sl, FLASH_F4_CR, sizeof (uint32_t));
+ }
+ else {
+ const uint32_t n = 1 << FLASH_CR_PG;
+ write_uint32(sl->q_buf, n);
+ stlink_write_mem32(sl, FLASH_CR, sizeof (uint32_t));
+ }
}
static void __attribute__((unused)) clear_flash_cr_pg(stlink_t *sl) {
const uint32_t n = read_flash_cr(sl) & ~(1 << FLASH_CR_PG);
write_uint32(sl->q_buf, n);
- stlink_write_mem32(sl, FLASH_CR, sizeof (uint32_t));
+ if(sl->chip_id==STM32F4_CHIP_ID)
+ stlink_write_mem32(sl, FLASH_F4_CR, sizeof (uint32_t));
+ else
+ stlink_write_mem32(sl, FLASH_CR, sizeof (uint32_t));
}
static void set_flash_cr_per(stlink_t *sl) {
}
static void set_flash_cr_strt(stlink_t *sl) {
- /* assume come on the flash_cr_per path */
- const uint32_t n = (1 << FLASH_CR_PER) | (1 << FLASH_CR_STRT);
- write_uint32(sl->q_buf, n);
- stlink_write_mem32(sl, FLASH_CR, sizeof (uint32_t));
+ if(sl->chip_id == STM32F4_CHIP_ID)
+ {
+ uint32_t x = read_flash_cr(sl);
+ x |= (1 << FLASH_F4_CR_STRT);
+ write_uint32(sl->q_buf, x);
+ stlink_write_mem32(sl, FLASH_F4_CR, sizeof (uint32_t));
+ }
+ else {
+ /* assume come on the flash_cr_per path */
+ const uint32_t n = (1 << FLASH_CR_PER) | (1 << FLASH_CR_STRT);
+ write_uint32(sl->q_buf, n);
+ stlink_write_mem32(sl, FLASH_CR, sizeof (uint32_t));
+ }
}
static inline uint32_t read_flash_acr(stlink_t *sl) {
}
static inline uint32_t read_flash_sr(stlink_t *sl) {
- stlink_read_mem32(sl, FLASH_SR, sizeof (uint32_t));
- return *(uint32_t*) sl->q_buf;
+ if(sl->chip_id==STM32F4_CHIP_ID)
+ stlink_read_mem32(sl, FLASH_F4_SR, sizeof (uint32_t));
+ else
+ stlink_read_mem32(sl, FLASH_SR, sizeof (uint32_t));
+ //fprintf(stdout, "SR:%X\n", *(uint32_t*) sl->q_buf);
+ return *(uint32_t*) sl->q_buf;
}
static inline unsigned int is_flash_busy(stlink_t *sl) {
- return read_flash_sr(sl) & (1 << FLASH_SR_BSY);
+ if(sl->chip_id==STM32F4_CHIP_ID)
+ return read_flash_sr(sl) & (1 << FLASH_F4_SR_BSY);
+ else
+ return read_flash_sr(sl) & (1 << FLASH_SR_BSY);
}
static void wait_flash_busy(stlink_t *sl) {
stlink_write_mem32(sl, FLASH_AR, sizeof (uint32_t));
}
+static inline void write_flash_cr_psiz(stlink_t *sl, uint32_t n) {
+ uint32_t x = read_flash_cr(sl);
+ x &= ~(0x03 << 8);
+ x |= (n << 8);
+ fprintf(stdout, "PSIZ:%X %X\n", x, n);
+ write_uint32(sl->q_buf, x);
+ stlink_write_mem32(sl, FLASH_F4_CR, sizeof (uint32_t));
+}
+
+
+static inline void write_flash_cr_snb(stlink_t *sl, uint32_t n) {
+ uint32_t x = read_flash_cr(sl);
+ x &= ~FLASH_F4_CR_SNB_MASK;
+ x |= (n << FLASH_F4_CR_SNB);
+ x |= (1 << FLASH_F4_CR_SER);
+ fprintf(stdout, "SNB:%X %X\n", x, n);
+ write_uint32(sl->q_buf, x);
+ stlink_write_mem32(sl, FLASH_F4_CR, sizeof (uint32_t));
+}
+
#if 0 /* todo */
static void disable_flash_read_protection(stlink_t *sl) {
void stlink_close(stlink_t *sl) {
D(sl, "\n*** stlink_close ***\n");
sl->backend->close(sl);
-
free(sl);
}
sl->backend->enter_swd_mode(sl);
}
+// Force the core into the debug mode -> halted state.
+void stlink_force_debug(stlink_t *sl) {
+ D(sl, "\n*** stlink_force_debug_mode ***\n");
+ sl->backend->force_debug(sl);
+}
+
void stlink_exit_dfu_mode(stlink_t *sl) {
D(sl, "\n*** stlink_exit_dfu_mode ***\n");
sl->backend->exit_dfu_mode(sl);
}
-void stlink_core_id(stlink_t *sl) {
+uint32_t stlink_core_id(stlink_t *sl) {
D(sl, "\n*** stlink_core_id ***\n");
sl->backend->core_id(sl);
if (sl->verbose > 2)
stlink_print_data(sl);
- DD(sl, "core_id = 0x%08x\n", sl->core_id);
+ return sl->core_id;
}
-uint16_t stlink_chip_id(stlink_t *sl) {
- stlink_read_mem32(sl, 0xE0042000, 4);
+void stlink_identify_device(stlink_t *sl) {
+ uint32_t core_id=stlink_core_id(sl);
+ stlink_read_mem32(sl, 0xE0042000, 4);
uint32_t chip_id = sl->q_buf[0] | (sl->q_buf[1] << 8) | (sl->q_buf[2] << 16) |
(sl->q_buf[3] << 24);
- return chip_id;
+ /* Fix chip_id for F4 */
+ if (((chip_id & 0xFFF) == 0x411) && (core_id == CORE_M4_R0)) {
+ printf("Fixing wrong chip_id for STM32F4 Rev A errata\n");
+ chip_id = 0x413;
+ }
+ sl->chip_id=chip_id;
+ sl->core_id=core_id;
+}
+
+/**
+ * Cortex m3 tech ref manual, CPUID register description
+ * @param sl stlink context
+ * @param cpuid pointer to the result object
+ */
+void stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid) {
+ stlink_read_mem32(sl, CM3_REG_CPUID, 4);
+ uint32_t raw = read_uint32(sl->q_buf, 0);
+ cpuid->implementer_id = (raw >> 24) & 0x7f;
+ cpuid->variant = (raw >> 20) & 0xf;
+ cpuid->part = (raw >> 4) & 0xfff;
+ cpuid->revision = raw & 0xf;
+ return;
}
void stlink_reset(stlink_t *sl) {
D(sl, "\n*** stlink_reset ***\n");
sl->backend->reset(sl);
-
}
void stlink_run(stlink_t *sl) {
char *p = (char *) &ui;
if (!is_bigendian()) { // le -> le (don't swap)
- p[0] = c[pt];
+ p[0] = c[pt + 0];
p[1] = c[pt + 1];
} else {
p[0] = c[pt + 1];
- p[1] = c[pt];
+ p[1] = c[pt + 0];
}
return ui;
}
if (sl->q_len <= 0)
return;
- stlink_print_data(sl);
-
switch (sl->q_buf[0]) {
case STLINK_CORE_RUNNING:
sl->core_stat = STLINK_CORE_RUNNING;
/* do the copy by 1k blocks */
for (off = 0; off < size; off += 1024) {
size_t read_size = 1024;
+ size_t rounded_size;
if ((off + read_size) > size)
- read_size = off + read_size;
+ read_size = size - off;
/* round size if needed */
- if (read_size & 3)
- read_size = (read_size + 4) & ~(3);
+ rounded_size = read_size;
+ if (rounded_size & 3)
+ rounded_size = (rounded_size + 4) & ~(3);
- stlink_read_mem32(sl, addr + off, read_size);
+ stlink_read_mem32(sl, addr + off, rounded_size);
if (write(fd, sl->q_buf, read_size) != (ssize_t) read_size) {
fprintf(stderr, "write() != read_size\n");
return 0;
}
-int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t page) {
- /* page an addr in the page to erase */
+uint32_t calculate_F4_sectornum(uint32_t flashaddr){
+ flashaddr &= ~STM32_FLASH_BASE; //Page now holding the actual flash address
+ if (flashaddr<0x4000) return (0);
+ else if(flashaddr<0x8000) return(1);
+ else if(flashaddr<0xc000) return(2);
+ else if(flashaddr<0x10000) return(3);
+ else if(flashaddr<0x20000) return(4);
+ else return(flashaddr/0x20000)+4;
+}
+
+uint32_t calculate_sectorsize(stlink_t *sl, uint32_t flashaddr){
+ if(sl->chip_id == STM32F4_CHIP_ID) {
+ uint32_t sector=calculate_F4_sectornum(flashaddr);
+ if (sector<4) return (0x4000);
+ else if(sector<5) return(0x10000);
+ else return(0x20000);
+ }
+ else return (sl->flash_pgsz);
+}
+
+int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t page)
+{
+ /* page an addr in the page to erase */
+
+ stlink_identify_device(sl);
+
+ if (sl->chip_id == STM32F4_CHIP_ID)
+ {
+ /* wait for ongoing op to finish */
+ wait_flash_busy(sl);
+
+ /* unlock if locked */
+ unlock_flash_if(sl);
+
+ /* select the page to erase */
+ //Page is passed to us as an addr, so calculate the actual page
+ uint32_t addr=page;
+
+ page=calculate_F4_sectornum(addr);
+
+ fprintf(stderr, "Erasing Sector:%u SectorSize:%u\n", page, calculate_sectorsize(sl, addr));
+ write_flash_cr_snb(sl, page);
+
+ /* start erase operation */
+ set_flash_cr_strt(sl);
+
+ /* wait for completion */
+ wait_flash_busy(sl);
+
+ /* relock the flash */
+ //todo: fails to program if this is in
+ lock_flash(sl);
+ fprintf(stdout, "Erase Final CR:%X\n", read_flash_cr(sl));
+
+ }
+
+ else if (sl->core_id == STM32L_CORE_ID)
+ {
+
+ uint32_t val;
+
+ /* disable pecr protection */
+ write_uint32(sl->q_buf, 0x89abcdef);
+ stlink_write_mem32(sl, STM32L_FLASH_PEKEYR, sizeof(uint32_t));
+ write_uint32(sl->q_buf, 0x02030405);
+ stlink_write_mem32(sl, STM32L_FLASH_PEKEYR, sizeof(uint32_t));
+
+ /* check pecr.pelock is cleared */
+ stlink_read_mem32(sl, STM32L_FLASH_PECR, sizeof(uint32_t));
+ val = read_uint32(sl->q_buf, 0);
+ if (val & (1 << 0))
+ {
+ fprintf(stderr, "pecr.pelock not clear (0x%x)\n", val);
+ return -1;
+ }
+
+ /* unlock program memory */
+ write_uint32(sl->q_buf, 0x8c9daebf);
+ stlink_write_mem32(sl, STM32L_FLASH_PRGKEYR, sizeof(uint32_t));
+ write_uint32(sl->q_buf, 0x13141516);
+ stlink_write_mem32(sl, STM32L_FLASH_PRGKEYR, sizeof(uint32_t));
+
+ /* check pecr.prglock is cleared */
+ stlink_read_mem32(sl, STM32L_FLASH_PECR, sizeof(uint32_t));
+ val = read_uint32(sl->q_buf, 0);
+ if (val & (1 << 1))
+ {
+ fprintf(stderr, "pecr.prglock not clear (0x%x)\n", val);
+ return -1;
+ }
+
+ /* unused: unlock the option byte block */
+#if 0
+ write_uint32(sl->q_buf, 0xfbead9c8);
+ stlink_write_mem32(sl, STM32L_FLASH_OPTKEYR, sizeof(uint32_t));
+ write_uint32(sl->q_buf, 0x24252627);
+ stlink_write_mem32(sl, STM32L_FLASH_OPTKEYR, sizeof(uint32_t));
+
+ /* check pecr.optlock is cleared */
+ stlink_read_mem32(sl, STM32L_FLASH_PECR, sizeof(uint32_t));
+ val = read_uint32(sl->q_buf, 0);
+ if (val & (1 << 2))
+ {
+ fprintf(stderr, "pecr.prglock not clear\n");
+ return -1;
+ }
+#endif
+
+ /* set pecr.{erase,prog} */
+ val |= (1 << 9) | (1 << 3);
+ write_uint32(sl->q_buf, val);
+ stlink_write_mem32(sl, STM32L_FLASH_PECR, sizeof(uint32_t));
+
+ /* wait for sr.busy to be cleared */
+ while (1)
+ {
+ stlink_read_mem32(sl, STM32L_FLASH_SR, sizeof(uint32_t));
+ if ((read_uint32(sl->q_buf, 0) & (1 << 0)) == 0) break ;
+ }
+
+ /* write 0 to the first word of the page to be erased */
+ memset(sl->q_buf, 0, sizeof(uint32_t));
+ stlink_write_mem32(sl, page, sizeof(uint32_t));
+
+ /* reset lock bits */
+ stlink_read_mem32(sl, STM32L_FLASH_PECR, sizeof(uint32_t));
+ val = read_uint32(sl->q_buf, 0) | (1 << 0) | (1 << 1) | (1 << 2);
+ write_uint32(sl->q_buf, val);
+ stlink_write_mem32(sl, STM32L_FLASH_PECR, sizeof(uint32_t));
+ }
+ else if (sl->core_id == STM32VL_CORE_ID)
+ {
/* wait for ongoing op to finish */
wait_flash_busy(sl);
/* relock the flash */
lock_flash(sl);
+ }
- /* todo: verify the erased page */
+ else {
+ fprintf(stderr, "unknown device!\n");
+ return -1;
+ }
- return 0;
+ /* todo: verify the erased page */
+
+ return 0;
}
int stlink_erase_flash_mass(stlink_t *sl) {
int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) {
/* from openocd, contrib/loaders/flash/stm32.s */
- static const uint8_t loader_code[] = {
+ static const uint8_t loader_code_stm32vl[] = {
0x08, 0x4c, /* ldr r4, STM32_FLASH_BASE */
0x1c, 0x44, /* add r4, r3 */
/* write_half_word: */
0x00, 0x20, 0x02, 0x40, /* STM32_FLASH_BASE: .word 0x40022000 */
};
- memcpy(sl->q_buf, loader_code, sizeof (loader_code));
- stlink_write_mem32(sl, sl->sram_base, sizeof (loader_code));
+ static const uint8_t loader_code_stm32l[] = {
+
+ /* openocd.git/contrib/loaders/flash/stm32lx.S
+ r0, input, dest addr
+ r1, input, source addr
+ r2, input, word count
+ r3, output, word count
+ */
+
+ 0x00, 0x23,
+ 0x04, 0xe0,
+
+ 0x51, 0xf8, 0x04, 0xcb,
+ 0x40, 0xf8, 0x04, 0xcb,
+ 0x01, 0x33,
+
+ 0x93, 0x42,
+ 0xf8, 0xd3,
+ 0x00, 0xbe
+ };
+
+ const uint8_t* loader_code;
+ size_t loader_size;
+
+ if (sl->core_id == STM32L_CORE_ID) /* stm32l */
+ {
+ loader_code = loader_code_stm32l;
+ loader_size = sizeof(loader_code_stm32l);
+ }
+ else if (sl->core_id == STM32VL_CORE_ID)
+ {
+ loader_code = loader_code_stm32vl;
+ loader_size = sizeof(loader_code_stm32vl);
+ }
+ else
+ {
+ fprintf(stderr, "unknown coreid: %x\n", sl->core_id);
+ return -1;
+ }
+
+ memcpy(sl->q_buf, loader_code, loader_size);
+ stlink_write_mem32(sl, sl->sram_base, loader_size);
*addr = sl->sram_base;
- *size = sizeof (loader_code);
+ *size = loader_size;
/* success */
return 0;
return res;
}
-// The stlink_fwrite_flash should not muck with mmapped files inside itself,
-// and should use this function instead. (Hell, what's the reason behind mmap
-// there?!) But, as it is not actually used anywhere, nobody cares.
-
-#define WRITE_BLOCK_SIZE 0x40
-
int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned len) {
size_t off;
flash_loader_t fl;
+ stlink_identify_device(sl);
+
+#if 0 /* todo: use in debugging mode only */
+ fprintf(stdout, "WriteFlash - addr:%x len:%x\n", addr, len);
+ fprintf(stdout, "CoreID:%X ChipID:%X\n", sl->core_id, sl->chip_id);
+#endif
+
/* check addr range is inside the flash */
if (addr < sl->flash_base) {
fprintf(stderr, "addr too low\n");
} else if ((addr & 1) || (len & 1)) {
fprintf(stderr, "unaligned addr or size\n");
return -1;
+ } else if (addr & (sl->flash_pgsz - 1)) {
+ fprintf(stderr, "addr not a multiple of pagesize, not supported\n");
+ return -1;
}
- /* flash loader initialization */
- if (init_flash_loader(sl, &fl) == -1) {
- fprintf(stderr, "init_flash_loader() == -1\n");
- return -1;
+ /* erase each page */
+ for (off = 0; off < len; off += calculate_sectorsize(sl, addr + off) ) {
+ /* addr must be an addr inside the page */
+ if (stlink_erase_flash_page(sl, addr + off) == -1) {
+ fprintf(stderr, "erase_flash_page(0x%zx) == -1\n", addr + off);
+ return -1;
+ }
}
- /* write each page. above WRITE_BLOCK_SIZE fails? */
- for (off = 0; off < len; off += WRITE_BLOCK_SIZE) {
- /* adjust last write size */
- size_t size = WRITE_BLOCK_SIZE;
- if ((off + WRITE_BLOCK_SIZE) > len)
- size = len - off;
+ if (sl->chip_id == STM32F4_CHIP_ID) {
+ /* todo: check write operation */
+
+ /* First unlock the cr */
+ unlock_flash_if(sl);
- if (run_flash_loader(sl, &fl, addr + off, base + off, size) == -1) {
- fprintf(stderr, "run_flash_loader(0x%zx) == -1\n", addr + off);
- return -1;
- }
+ /* set parallelisim to 32 bit*/
+ write_flash_cr_psiz(sl, 2);
+
+ /* set programming mode */
+ set_flash_cr_pg(sl);
+
+#define PROGRESS_CHUNK_SIZE 0x1000
+ /* write a word in program memory */
+ for (off = 0; off < len; off += sizeof(uint32_t)) {
+ if (sl->verbose >= 1) {
+ if ((off & (PROGRESS_CHUNK_SIZE - 1)) == 0) {
+ /* show progress. writing procedure is slow
+ and previous errors are misleading */
+ const uint32_t pgnum = (off / PROGRESS_CHUNK_SIZE)+1;
+ const uint32_t pgcount = len / PROGRESS_CHUNK_SIZE;
+ fprintf(stdout, "Writing %ukB chunk %u out of %u\n", PROGRESS_CHUNK_SIZE/1024, pgnum, pgcount);
+ }
+ }
+
+ memcpy(sl->q_buf, (const void*)(base + off), sizeof(uint32_t));
+ stlink_write_mem32(sl, addr + off, sizeof(uint32_t));
+
+ /* wait for sr.busy to be cleared */
+ wait_flash_busy(sl);
+
+ }
+ /* Relock flash */
+ lock_flash(sl);
+
+#if 0 /* todo: debug mode */
+ fprintf(stdout, "Final CR:%X\n", read_flash_cr(sl));
+#endif
+
+
+
+ } //STM32F4END
+
+ else if (sl->core_id == STM32L_CORE_ID) {
+ /* use fast word write. todo: half page. */
+
+ uint32_t val;
+
+#if 0 /* todo: check write operation */
+
+ uint32_t nwrites = sl->flash_pgsz;
+
+ redo_write:
+
+#endif /* todo: check write operation */
+
+ /* disable pecr protection */
+ write_uint32(sl->q_buf, 0x89abcdef);
+ stlink_write_mem32(sl, STM32L_FLASH_PEKEYR, sizeof(uint32_t));
+ write_uint32(sl->q_buf, 0x02030405);
+ stlink_write_mem32(sl, STM32L_FLASH_PEKEYR, sizeof(uint32_t));
+
+ /* check pecr.pelock is cleared */
+ stlink_read_mem32(sl, STM32L_FLASH_PECR, sizeof(uint32_t));
+ val = read_uint32(sl->q_buf, 0);
+ if (val & (1 << 0)) {
+ fprintf(stderr, "pecr.pelock not clear\n");
+ return -1;
+ }
+
+ /* unlock program memory */
+ write_uint32(sl->q_buf, 0x8c9daebf);
+ stlink_write_mem32(sl, STM32L_FLASH_PRGKEYR, sizeof(uint32_t));
+ write_uint32(sl->q_buf, 0x13141516);
+ stlink_write_mem32(sl, STM32L_FLASH_PRGKEYR, sizeof(uint32_t));
+
+ /* check pecr.prglock is cleared */
+ stlink_read_mem32(sl, STM32L_FLASH_PECR, sizeof(uint32_t));
+ val = read_uint32(sl->q_buf, 0);
+ if (val & (1 << 1)) {
+ fprintf(stderr, "pecr.prglock not clear\n");
+ return -1;
+ }
+
+ /* write a word in program memory */
+ for (off = 0; off < len; off += sizeof(uint32_t)) {
+ if (sl->verbose >= 1) {
+ if ((off & (sl->flash_pgsz - 1)) == 0) {
+ /* show progress. writing procedure is slow
+ and previous errors are misleading */
+ const uint32_t pgnum = off / sl->flash_pgsz;
+ const uint32_t pgcount = len / sl->flash_pgsz;
+ fprintf(stdout, "%u pages written out of %u\n", pgnum, pgcount);
+ }
+ }
+
+ memcpy(sl->q_buf, (const void*)(base + off), sizeof(uint32_t));
+ stlink_write_mem32(sl, addr + off, sizeof(uint32_t));
+
+ /* wait for sr.busy to be cleared */
+ while (1) {
+ stlink_read_mem32(sl, STM32L_FLASH_SR, sizeof(uint32_t));
+ if ((read_uint32(sl->q_buf, 0) & (1 << 0)) == 0) break ;
+ }
+
+#if 0 /* todo: check redo write operation */
+
+ /* check written bytes. todo: should be on a per page basis. */
+ stlink_read_mem32(sl, addr + off, sizeof(uint32_t));
+ if (memcmp(sl->q_buf, base + off, sizeof(uint32_t))) {
+ /* re erase the page and redo the write operation */
+ uint32_t page;
+ uint32_t val;
+
+ /* fail if successive write count too low */
+ if (nwrites < sl->flash_pgsz) {
+ fprintf(stderr, "writes operation failure count too high, aborting\n");
+ return -1;
+ }
+
+ nwrites = 0;
+
+ /* assume addr aligned */
+ if (off % sl->flash_pgsz) off &= ~(sl->flash_pgsz - 1);
+ page = addr + off;
+
+ fprintf(stderr, "invalid write @%x(%x): %x != %x. retrying.\n",
+ page, addr + off, read_uint32(base + off, 0), read_uint32(sl->q_buf, 0));
+
+ /* reset lock bits */
+ stlink_read_mem32(sl, STM32L_FLASH_PECR, sizeof(uint32_t));
+ val = read_uint32(sl->q_buf, 0) | (1 << 0) | (1 << 1) | (1 << 2);
+ write_uint32(sl->q_buf, val);
+ stlink_write_mem32(sl, STM32L_FLASH_PECR, sizeof(uint32_t));
+
+ stlink_erase_flash_page(sl, page);
+
+ goto redo_write;
+ }
+
+ /* increment successive writes counter */
+ ++nwrites;
+
+#endif /* todo: check redo write operation */
+ }
+ /* reset lock bits */
+ stlink_read_mem32(sl, STM32L_FLASH_PECR, sizeof(uint32_t));
+ val = read_uint32(sl->q_buf, 0) | (1 << 0) | (1 << 1) | (1 << 2);
+ write_uint32(sl->q_buf, val);
+ stlink_write_mem32(sl, STM32L_FLASH_PECR, sizeof(uint32_t));
+ }
+
+
+
+
+ else if (sl->core_id == STM32VL_CORE_ID) {
+ /* flash loader initialization */
+ if (init_flash_loader(sl, &fl) == -1) {
+ fprintf(stderr, "init_flash_loader() == -1\n");
+ return -1;
+ }
+ /* write each page. above WRITE_BLOCK_SIZE fails? */
+#define WRITE_BLOCK_SIZE 0x40
+ for (off = 0; off < len; off += WRITE_BLOCK_SIZE) {
+ /* adjust last write size */
+ size_t size = WRITE_BLOCK_SIZE;
+ if ((off + WRITE_BLOCK_SIZE) > len) size = len - off;
+
+ /* unlock and set programming mode */
+ unlock_flash_if(sl);
+ set_flash_cr_pg(sl);
+
+ if (run_flash_loader(sl, &fl, addr + off, base + off, size) == -1) {
+ fprintf(stderr, "run_flash_loader(0x%zx) == -1\n", addr + off);
+ return -1;
+ }
+ lock_flash(sl);
+ }
}
+
+
+
+ else
+ {
+ fprintf(stderr, "unknown device!\n");
+ return -1;
+ }
+
+
+
+
+
+#if(0)
+ //todo: F4 Can't stlink_read_mem32 an entire sector, not enough ram!
for (off = 0; off < len; off += sl->flash_pgsz) {
size_t aligned_size;
if (aligned_size & (4 - 1))
aligned_size = (cmp_size + 4) & ~(4 - 1);
+ fprintf(stdout, "AlignedSize:%x\n", aligned_size);
stlink_read_mem32(sl, addr + off, aligned_size);
if (memcmp(sl->q_buf, base + off, cmp_size))
return -1;
}
+#endif
return 0;
}
+
+
+
int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr) {
/* write the file in flash at addr */
- int error = -1;
- size_t off;
+ int err;
mapped_file_t mf = MAPPED_FILE_INITIALIZER;
- flash_loader_t fl;
if (map_file(&mf, path) == -1) {
fprintf(stderr, "map_file() == -1\n");
return -1;
}
- /* check addr range is inside the flash */
- if (addr < sl->flash_base) {
- fprintf(stderr, "addr too low\n");
- goto on_error;
- } else if ((addr + mf.len) < addr) {
- fprintf(stderr, "addr overruns\n");
- goto on_error;
- } else if ((addr + mf.len) > (sl->flash_base + sl->flash_size)) {
- fprintf(stderr, "addr too high\n");
- goto on_error;
- } else if ((addr & 1) || (mf.len & 1)) {
- /* todo */
- fprintf(stderr, "unaligned addr or size\n");
- goto on_error;
- }
+ err = stlink_write_flash(sl, addr, mf.base, mf.len);
- /* erase each page. todo: mass erase faster? */
- for (off = 0; off < mf.len; off += sl->flash_pgsz) {
- /* addr must be an addr inside the page */
- if (stlink_erase_flash_page(sl, addr + off) == -1) {
- fprintf(stderr, "erase_flash_page(0x%zx) == -1\n", addr + off);
- goto on_error;
- }
- }
-
- /* flash loader initialization */
- if (init_flash_loader(sl, &fl) == -1) {
- fprintf(stderr, "init_flash_loader() == -1\n");
- goto on_error;
- }
-
- /* write each page. above WRITE_BLOCK_SIZE fails? */
-#define WRITE_BLOCK_SIZE 0x40
- for (off = 0; off < mf.len; off += WRITE_BLOCK_SIZE) {
- /* adjust last write size */
- size_t size = WRITE_BLOCK_SIZE;
- if ((off + WRITE_BLOCK_SIZE) > mf.len)
- size = mf.len - off;
-
- if (run_flash_loader(sl, &fl, addr + off, mf.base + off, size) == -1) {
- fprintf(stderr, "run_flash_loader(0x%zx) == -1\n", addr + off);
- goto on_error;
- }
- }
-
- /* check the file ha been written */
- if (check_file(sl, &mf, addr) == -1) {
- fprintf(stderr, "check_file() == -1\n");
- goto on_error;
- }
-
- /* success */
- error = 0;
-
-on_error:
unmap_file(&mf);
- return error;
+
+ return err;
}
int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, const uint8_t* buf, size_t size) {
- const size_t count = size / sizeof (uint16_t);
+
+ reg rr;
if (write_buffer_to_sram(sl, fl, buf, size) == -1) {
fprintf(stderr, "write_buffer_to_sram() == -1\n");
return -1;
}
- /* setup core */
- stlink_write_reg(sl, fl->buf_addr, 0); /* source */
- stlink_write_reg(sl, target, 1); /* target */
- stlink_write_reg(sl, count, 2); /* count (16 bits half words) */
- stlink_write_reg(sl, 0, 3); /* flash bank 0 (input) */
- stlink_write_reg(sl, fl->loader_addr, 15); /* pc register */
+ if (sl->core_id == STM32L_CORE_ID) {
- /* unlock and set programming mode */
- unlock_flash_if(sl);
- set_flash_cr_pg(sl);
+ size_t count = size / sizeof(uint32_t);
+ if (size % sizeof(uint32_t)) ++count;
+
+ /* setup core */
+ stlink_write_reg(sl, target, 0); /* target */
+ stlink_write_reg(sl, fl->buf_addr, 1); /* source */
+ stlink_write_reg(sl, count, 2); /* count (32 bits words) */
+ stlink_write_reg(sl, 0, 3); /* output count */
+ stlink_write_reg(sl, fl->loader_addr, 15); /* pc register */
+
+ } else if (sl->core_id == STM32VL_CORE_ID) {
+
+ size_t count = size / sizeof(uint16_t);
+ if (size % sizeof(uint16_t)) ++count;
+
+ /* setup core */
+ stlink_write_reg(sl, fl->buf_addr, 0); /* source */
+ stlink_write_reg(sl, target, 1); /* target */
+ stlink_write_reg(sl, count, 2); /* count (16 bits half words) */
+ stlink_write_reg(sl, 0, 3); /* flash bank 0 (input) */
+ stlink_write_reg(sl, fl->loader_addr, 15); /* pc register */
+
+ } else {
+ fprintf(stderr, "unknown coreid: %x\n", sl->core_id);
+ return -1;
+ }
/* run loader */
- stlink_run(sl);
+ stlink_step(sl);
- while (is_core_halted(sl) == 0)
- ;
+ /* wait until done (reaches breakpoint) */
+ while (is_core_halted(sl) == 0) ;
- lock_flash(sl);
+ /* check written byte count */
+ if (sl->core_id == STM32L_CORE_ID) {
- /* not all bytes have been written */
- reg rr;
- stlink_read_reg(sl, 2, &rr);
- if (rr.r[2] != 0) {
+ size_t count = size / sizeof(uint32_t);
+ if (size % sizeof(uint32_t)) ++count;
+
+ stlink_read_reg(sl, 3, &rr);
+ if (rr.r[3] != count) {
+ fprintf(stderr, "write error, count == %u\n", rr.r[3]);
+ return -1;
+ }
+
+ } else if (sl->core_id == STM32VL_CORE_ID) {
+
+ stlink_read_reg(sl, 2, &rr);
+ if (rr.r[2] != 0) {
fprintf(stderr, "write error, count == %u\n", rr.r[2]);
return -1;
+ }
+
+ } else {
+
+ fprintf(stderr, "unknown coreid: %x\n", sl->core_id);
+ return -1;
+
}
return 0;
-}
\ No newline at end of file
+}
projects / fw / stlink / blobdiff