static uint32_t __attribute__((unused)) read_flash_rdp(stlink_t *sl) {
stlink_read_mem32(sl, FLASH_WRPR, sizeof (uint32_t));
- return (*(uint32_t*) sl->q_buf) & 0xff;
+ return read_uint32(sl->q_buf, 0) & 0xff;
}
static inline uint32_t read_flash_wrpr(stlink_t *sl) {
stlink_read_mem32(sl, FLASH_WRPR, sizeof (uint32_t));
- return *(uint32_t*) sl->q_buf;
+ return read_uint32(sl->q_buf, 0);
}
static inline uint32_t read_flash_obr(stlink_t *sl) {
stlink_read_mem32(sl, FLASH_OBR, sizeof (uint32_t));
- return *(uint32_t*) sl->q_buf;
+ return read_uint32(sl->q_buf, 0);
}
static inline uint32_t read_flash_cr(stlink_t *sl) {
#if DEBUG_FLASH
fprintf(stdout, "CR:0x%x\n", *(uint32_t*) sl->q_buf);
#endif
- return *(uint32_t*) sl->q_buf;
+ return read_uint32(sl->q_buf, 0);
}
static inline unsigned int is_flash_locked(stlink_t *sl) {
static inline uint32_t read_flash_acr(stlink_t *sl) {
stlink_read_mem32(sl, FLASH_ACR, sizeof (uint32_t));
- return *(uint32_t*) sl->q_buf;
+ return read_uint32(sl->q_buf, 0);
}
static inline uint32_t read_flash_sr(stlink_t *sl) {
else
stlink_read_mem32(sl, FLASH_SR, sizeof (uint32_t));
//fprintf(stdout, "SR:0x%x\n", *(uint32_t*) sl->q_buf);
- return *(uint32_t*) sl->q_buf;
+ return read_uint32(sl->q_buf, 0);
}
static inline unsigned int is_flash_busy(stlink_t *sl) {
sl->sys_base = params->bootrom_base;
sl->sys_size = params->bootrom_size;
- ILOG("Device connected is: %s\n", params->description);
+ ILOG("Device connected is: %s, id %#x\n", params->description, chip_id);
// TODO make note of variable page size here.....
ILOG("SRAM size: %#x bytes (%d KiB), Flash: %#x bytes (%d KiB) in pages of %zd bytes\n",
sl->sram_size, sl->sram_size / 1024, sl->flash_size, sl->flash_size / 1024,
sl->backend->reset(sl);
}
+void stlink_jtag_reset(stlink_t *sl, int value) {
+ DLOG("*** stlink_jtag_reset ***\n");
+ sl->backend->jtag_reset(sl, value);
+}
+
void stlink_run(stlink_t *sl) {
DLOG("*** stlink_run ***\n");
sl->backend->run(sl);
}
}
+uint32_t stlink_read_debug32(stlink_t *sl, uint32_t addr) {
+ uint32_t data = sl->backend->read_debug32(sl, addr);
+ DLOG("*** stlink_read_debug32 %x is %#x\n", data, addr);
+ return data;
+}
+
+void stlink_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data) {
+ DLOG("*** stlink_write_debug32 %x to %#x\n", data, addr);
+ sl->backend->write_debug32(sl, addr, data);
+}
+
void stlink_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) {
DLOG("*** stlink_write_mem32 %u bytes to %#x\n", len, addr);
if (len % 4 != 0) {
write_uint32(sl->q_buf, val);
stlink_write_mem32(sl, STM32L_FLASH_PECR, sizeof(uint32_t));
- /* wait for sr.busy to be cleared */
+#if 0 /* fix_to_be_confirmed */
+
+ /* wait for sr.busy to be cleared
+ MP: Test shows that busy bit is not set here. Perhaps, PM0062 is
+ wrong and we do not need to wait here for clearing the busy bit.
+ TEXANE: ok, if experience says so and it works for you, we comment
+ it. If someone has a problem, please drop an email.
+ */
while (1)
{
stlink_read_mem32(sl, STM32L_FLASH_SR, sizeof(uint32_t));
if ((read_uint32(sl->q_buf, 0) & (1 << 0)) == 0) break ;
}
+#endif /* fix_to_be_confirmed */
+
/* write 0 to the first word of the page to be erased */
memset(sl->q_buf, 0, sizeof(uint32_t));
stlink_write_mem32(sl, flashaddr, sizeof(uint32_t));
+ /* MP: It is better to wait for clearing the busy bit after issuing
+ page erase command, even though PM0062 recommends to wait before it.
+ Test shows that a few iterations is performed in the following loop
+ before busy bit is cleared.*/
+ while (1)
+ {
+ stlink_read_mem32(sl, STM32L_FLASH_SR, sizeof(uint32_t));
+ if ((read_uint32(sl->q_buf, 0) & (1 << 0)) == 0) break;
+ }
+
/* reset lock bits */
stlink_read_mem32(sl, STM32L_FLASH_PECR, sizeof(uint32_t));
val = read_uint32(sl->q_buf, 0) | (1 << 0) | (1 << 1) | (1 << 2);
return res;
}
+/**
+ * Verify addr..addr+len is binary identical to base...base+len
+ * @param sl stlink context
+ * @param address stm device address
+ * @param data host side buffer to check against
+ * @param length how much
+ * @return 0 for success, -ve for failure
+ */
+int stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, unsigned length) {
+ size_t off;
+ if ((sl->chip_id & 0xFFF) == STM32_CHIPID_F4) {
+ DLOG("(FIXME)Skipping verification for F4, not enough ram (yet)\n");
+ return 0;
+ }
+ ILOG("Starting verification of write complete\n");
+ for (off = 0; off < length; off += sl->flash_pgsz) {
+ size_t aligned_size;
+
+ /* adjust last page size */
+ size_t cmp_size = sl->flash_pgsz;
+ if ((off + sl->flash_pgsz) > length)
+ cmp_size = length - off;
+
+ aligned_size = cmp_size;
+ if (aligned_size & (4 - 1))
+ aligned_size = (cmp_size + 4) & ~(4 - 1);
+
+ stlink_read_mem32(sl, address + off, aligned_size);
+
+ if (memcmp(sl->q_buf, data + off, cmp_size)) {
+ WLOG("Verification of flash failed at offset: %zd\n", off);
+ return -1;
+ }
+ }
+ ILOG("Flash written and verified! jolly good!\n");
+ return 0;
+
+}
+
int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned len) {
size_t off;
flash_loader_t fl;
else if (sl->core_id == STM32L_CORE_ID) {
/* use fast word write. todo: half page. */
-
uint32_t val;
#if 0 /* todo: check write operation */
WLOG("unknown coreid, not sure how to write: %x\n", sl->core_id);
return -1;
}
-
- ILOG("Starting verification of write complete\n");
- for (off = 0; off < len; off += sl->flash_pgsz) {
- size_t aligned_size;
-
- /* adjust last page size */
- size_t cmp_size = sl->flash_pgsz;
- if ((off + sl->flash_pgsz) > len)
- cmp_size = len - off;
-
- aligned_size = cmp_size;
- if (aligned_size & (4 - 1))
- aligned_size = (cmp_size + 4) & ~(4 - 1);
-
- fprintf(stdout, "AlignedSize:%#zx\n", aligned_size);
- stlink_read_mem32(sl, addr + off, aligned_size);
-
- if (memcmp(sl->q_buf, base + off, cmp_size))
- return -1;
- }
- ILOG("Flash written and verified! jolly good!\n");
- return 0;
+
+ return stlink_verify_write_flash(sl, addr, base, len);
}
/**
projects / fw / stlink / blobdiff