}
+/* todo: stm32l15xxx flash memory, pm0062 manual */
+/* #define FLASH_REGS_ADDR 0x40022000 */
-/* FPEC flash controller interface, pm0063 manual
- */
+/* stm32f FPEC flash controller interface, pm0063 manual */
#define FLASH_REGS_ADDR 0x40022000
#define FLASH_REGS_SIZE 0x28
void stlink_close(stlink_t *sl) {
D(sl, "\n*** stlink_close ***\n");
sl->backend->close(sl);
-
free(sl);
}
sl->backend->enter_swd_mode(sl);
}
+// Force the core into the debug mode -> halted state.
+void stlink_force_debug(stlink_t *sl) {
+ D(sl, "\n*** stlink_force_debug_mode ***\n");
+ sl->backend->force_debug(sl);
+}
+
void stlink_exit_dfu_mode(stlink_t *sl) {
D(sl, "\n*** stlink_exit_dfu_mode ***\n");
sl->backend->exit_dfu_mode(sl);
}
-void stlink_core_id(stlink_t *sl) {
+uint32_t stlink_core_id(stlink_t *sl) {
D(sl, "\n*** stlink_core_id ***\n");
sl->backend->core_id(sl);
+ if (sl->verbose > 2)
+ stlink_print_data(sl);
DD(sl, "core_id = 0x%08x\n", sl->core_id);
+ return sl->core_id;
+}
+
+uint16_t stlink_chip_id(stlink_t *sl) {
+ stlink_read_mem32(sl, 0xE0042000, 4);
+ uint32_t chip_id = sl->q_buf[0] | (sl->q_buf[1] << 8) | (sl->q_buf[2] << 16) |
+ (sl->q_buf[3] << 24);
+ return chip_id;
+}
+
+/**
+ * Cortex m3 tech ref manual, CPUID register description
+ * @param sl stlink context
+ * @param cpuid pointer to the result object
+ */
+void stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid) {
+ stlink_read_mem32(sl, CM3_REG_CPUID, 4);
+ uint32_t raw = read_uint32(sl->q_buf, 0);
+ cpuid->implementer_id = (raw >> 24) & 0x7f;
+ cpuid->variant = (raw >> 20) & 0xf;
+ cpuid->part = (raw >> 4) & 0xfff;
+ cpuid->revision = raw & 0xf;
+ return;
}
void stlink_reset(stlink_t *sl) {
D(sl, "\n*** stlink_reset ***\n");
sl->backend->reset(sl);
-
}
void stlink_run(stlink_t *sl) {
stlink_core_stat(sl);
}
+/**
+ * Decode the version bits, originally from -sg, verified with usb
+ * @param sl stlink context, assumed to contain valid data in the buffer
+ * @param slv output parsed version object
+ */
+void _parse_version(stlink_t *sl, stlink_version_t *slv) {
+ uint32_t b0 = sl->q_buf[0]; //lsb
+ uint32_t b1 = sl->q_buf[1];
+ uint32_t b2 = sl->q_buf[2];
+ uint32_t b3 = sl->q_buf[3];
+ uint32_t b4 = sl->q_buf[4];
+ uint32_t b5 = sl->q_buf[5]; //msb
+
+ // b0 b1 || b2 b3 | b4 b5
+ // 4b | 6b | 6b || 2B | 2B
+ // stlink_v | jtag_v | swim_v || st_vid | stlink_pid
+
+ slv->stlink_v = (b0 & 0xf0) >> 4;
+ slv->jtag_v = ((b0 & 0x0f) << 2) | ((b1 & 0xc0) >> 6);
+ slv->swim_v = b1 & 0x3f;
+ slv->st_vid = (b3 << 8) | b2;
+ slv->stlink_pid = (b5 << 8) | b4;
+ return;
+}
+
void stlink_version(stlink_t *sl) {
D(sl, "*** looking up stlink version\n");
+ stlink_version_t slv;
sl->backend->version(sl);
+ _parse_version(sl, &slv);
+
+ DD(sl, "st vid = 0x%04x (expect 0x%04x)\n", slv.st_vid, USB_ST_VID);
+ DD(sl, "stlink pid = 0x%04x\n", slv.stlink_pid);
+ DD(sl, "stlink version = 0x%x\n", slv.stlink_v);
+ DD(sl, "jtag version = 0x%x\n", slv.jtag_v);
+ DD(sl, "swim version = 0x%x\n", slv.swim_v);
+ if (slv.jtag_v == 0) {
+ DD(sl, " notice: the firmware doesn't support a jtag/swd interface\n");
+ }
+ if (slv.swim_v == 0) {
+ DD(sl, " notice: the firmware doesn't support a swim interface\n");
+ }
}
void stlink_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) {
sl->backend->write_mem8(sl, addr, len);
}
-void stlink_read_all_reg(stlink_t *sl) {
- D(sl, "\n*** stlink_read_all_reg ***\n");
- sl->backend->read_all_reg(sl);
+void stlink_read_all_regs(stlink_t *sl, reg *regp) {
+ D(sl, "\n*** stlink_read_all_regs ***\n");
+ sl->backend->read_all_regs(sl, regp);
}
void stlink_write_reg(stlink_t *sl, uint32_t reg, int idx) {
}
int stlink_current_mode(stlink_t *sl) {
- D(sl, "\n*** stlink_current_mode ***\n");
int mode = sl->backend->current_mode(sl);
- stlink_print_data(sl);
switch (mode) {
case STLINK_DEV_DFU_MODE:
- DD(sl, "stlink mode: dfu\n");
+ DD(sl, "stlink current mode: dfu\n");
return mode;
case STLINK_DEV_DEBUG_MODE:
- DD(sl, "stlink mode: debug (jtag or swd)\n");
+ DD(sl, "stlink current mode: debug (jtag or swd)\n");
return mode;
case STLINK_DEV_MASS_MODE:
- DD(sl, "stlink mode: mass\n");
+ DD(sl, "stlink current mode: mass\n");
return mode;
}
DD(sl, "stlink mode: unknown!\n");
int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) {
/* from openocd, contrib/loaders/flash/stm32.s */
- static const uint8_t loader_code[] = {
+ static const uint8_t loader_code_stm32vl[] = {
0x08, 0x4c, /* ldr r4, STM32_FLASH_BASE */
0x1c, 0x44, /* add r4, r3 */
/* write_half_word: */
0x00, 0x20, 0x02, 0x40, /* STM32_FLASH_BASE: .word 0x40022000 */
};
- memcpy(sl->q_buf, loader_code, sizeof (loader_code));
- stlink_write_mem32(sl, sl->sram_base, sizeof (loader_code));
+ static const uint8_t loader_code_stm32l[] = {
+ /* see openocd.git/contib/loaders/flash/stm32lx.s for src */
+ 0x00, 0x23,
+ 0x04, 0xe0,
+
+ 0x51, 0xf8, 0x04, 0xcb,
+ 0x40, 0xf8, 0x04, 0xcb,
+ 0x01, 0x33,
+
+ 0x93, 0x42,
+ 0xf8, 0xd3,
+ 0x00, 0xbe
+ };
+
+ const uint8_t* loader_code;
+ size_t loader_size;
+
+ if (sl->core_id == 0x2ba01477) /* stm32l */
+ {
+ loader_code = loader_code_stm32l;
+ loader_size = sizeof(loader_code_stm32l);
+ }
+ else /* stm32vl */
+ {
+ loader_code = loader_code_stm32vl;
+ loader_size = sizeof(loader_code_stm32vl);
+ }
+
+ memcpy(sl->q_buf, loader_code, loader_size);
+ stlink_write_mem32(sl, sl->sram_base, loader_size);
*addr = sl->sram_base;
- *size = sizeof (loader_code);
+ *size = loader_size;
/* success */
return 0;
return -1;
}
+ /* needed for specializing loader */
+ stlink_core_id(sl);
+
/* flash loader initialization */
if (init_flash_loader(sl, &fl) == -1) {
fprintf(stderr, "init_flash_loader() == -1\n");
goto on_error;
}
+ /* needed for specializing loader */
+ stlink_core_id(sl);
+
/* erase each page. todo: mass erase faster? */
for (off = 0; off < mf.len; off += sl->flash_pgsz) {
/* addr must be an addr inside the page */
}
return 0;
-}
\ No newline at end of file
+}
projects / fw / stlink / blobdiff