Align loader to 32-bit boundary

[fw/stlink] / src / stlink-common.c

diff --git a/src/stlink-common.c b/src/stlink-common.c
index a1ccdfdcc70bc63c44e41090f24ad5b3dc2dcdb8..533e670c6969dfa130039ab9117eab2a6dfe4999 100644 (file)
--- a/src/stlink-common.c
+++ b/src/stlink-common.c
@@ -251,7 +251,7 @@ static void lock_flash(stlink_t *sl) {
 
     if (sl->flash_type == FLASH_TYPE_F4) {
         cr_reg = FLASH_F4_CR;
-        cr_lock_shift = STM32L4_FLASH_CR_LOCK;
+        cr_lock_shift = FLASH_F4_CR_LOCK;
     } else if (sl->flash_type == FLASH_TYPE_L4) {
         cr_reg = STM32L4_FLASH_CR;
         cr_lock_shift = STM32L4_FLASH_CR_LOCK;
@@ -481,6 +481,8 @@ static inline void write_flash_cr_bker_pnb(stlink_t *sl, uint32_t n) {
 
 void stlink_close(stlink_t *sl) {
     DLOG("*** stlink_close ***\n");
+    if (!sl)
+         return;
     sl->backend->close(sl);
     free(sl);
 }
@@ -534,7 +536,7 @@ int stlink_chip_id(stlink_t *sl, uint32_t *chip_id) {
     if (ret == -1)
         return ret;
 
-    if (chip_id == 0)
+    if (*chip_id == 0)
         ret = stlink_read_debug32(sl, 0x40015800, chip_id);    //Try Corex M0 DBGMCU_IDCODE register address
 
     return ret;
@@ -708,7 +710,7 @@ int stlink_version(stlink_t *sl) {
         DLOG("    notice: the firmware doesn't support a swim interface\n");
     }
 
-    return -1;
+    return 0;
 }
 
 int stlink_target_voltage(stlink_t *sl) {
@@ -732,7 +734,7 @@ int stlink_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data) {
 
     ret = sl->backend->read_debug32(sl, addr, data);
     if (!ret)
-           DLOG("*** stlink_read_debug32 %x is %#x\n", data, addr);
+           DLOG("*** stlink_read_debug32 %x is %#x\n", *data, addr);
 
        return ret;
 }
@@ -1197,7 +1199,7 @@ uint32_t calculate_L4_page(stlink_t *sl, uint32_t flashaddr) {
     flashaddr -= STM32_FLASH_BASE;
     if (flashopt & (1lu << STM32L4_FLASH_OPTR_DUALBANK)) {
         uint32_t banksize = sl->flash_size / 2;
-        if (flashaddr > banksize) {
+        if (flashaddr >= banksize) {
             flashaddr -= banksize;
             bker = 0x100;
         }
@@ -1248,19 +1250,21 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr)
             // calculate the actual bank+page from the address
             uint32_t page = calculate_L4_page(sl, flashaddr);
 
+            fprintf(stderr, "EraseFlash - Page:0x%x Size:0x%x ", page, stlink_calculate_pagesize(sl, flashaddr));
+
             write_flash_cr_bker_pnb(sl, page);
         } else if (sl->chip_id == STM32_CHIPID_F7) {
             // calculate the actual page from the address
             uint32_t sector=calculate_F7_sectornum(flashaddr);
 
-            fprintf(stderr, "EraseFlash - Sector:0x%x Size:0x%x\n", sector, stlink_calculate_pagesize(sl, flashaddr));
+            fprintf(stderr, "EraseFlash - Sector:0x%x Size:0x%x ", sector, stlink_calculate_pagesize(sl, flashaddr));
 
             write_flash_cr_snb(sl, sector);
         } else {
             // calculate the actual page from the address
             uint32_t sector=calculate_F4_sectornum(flashaddr);
 
-            fprintf(stderr, "EraseFlash - Sector:0x%x Size:0x%x\n", sector, stlink_calculate_pagesize(sl, flashaddr));
+            fprintf(stderr, "EraseFlash - Sector:0x%x Size:0x%x ", sector, stlink_calculate_pagesize(sl, flashaddr));
         
             //the SNB values for flash sectors in the second bank do not directly follow the values for the first bank on 2mb devices...
             if (sector >= 12) sector += 4;
@@ -1390,7 +1394,7 @@ int stlink_erase_flash_mass(stlink_t *sl) {
                 WLOG("Failed to erase_flash_page(%#zx) == -1\n", addr);
                 return -1;
             }
-            fprintf(stdout,"\rFlash page at %5d/%5d erased", i, num_pages);
+            fprintf(stdout,"-> Flash page at %5d/%5d erased\n", i, num_pages);
             fflush(stdout);
         }
         fprintf(stdout, "\n");
@@ -1521,7 +1525,7 @@ int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) {
 
         0x00, 0x2a,
         0xf8, 0xd3,
-        0x00, 0xbe
+        0x00, 0xbe,
     };
 
     static const uint8_t loader_code_stm32l0[] = {
@@ -1543,7 +1547,7 @@ int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) {
 
         0x00, 0x2a,
         0xf8, 0xd3,
-        0x00, 0xbe
+        0x00, 0xbe,
     };
 
     static const uint8_t loader_code_stm32f4[] = {
@@ -1675,6 +1679,10 @@ int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) {
     }
 
     memcpy(sl->q_buf, loader_code, loader_size);
+
+    /* pad to 32-bits */
+    loader_size = (loader_size + 3) & ~3;
+
     stlink_write_mem32(sl, sl->sram_base, loader_size);
 
     *addr = sl->sram_base;