#define O_BINARY 0
#endif
-
-#define LOG_TAG __FILE__
-#define DLOG(format, args...) ugly_log(UDEBUG, LOG_TAG, format, ## args)
-#define ILOG(format, args...) ugly_log(UINFO, LOG_TAG, format, ## args)
-#define WLOG(format, args...) ugly_log(UWARN, LOG_TAG, format, ## args)
-#define ELOG(format, args...) ugly_log(UERROR, LOG_TAG, format, ## args)
-#define fatal(format, args...) ugly_log(UFATAL, LOG_TAG, format, ## args)
-
/* todo: stm32l15xxx flash memory, pm0062 manual */
/* stm32f FPEC flash controller interface, pm0063 manual */
#define FLASH_L1_FPRG 10
#define FLASH_L1_PROG 3
+//32L4 register base is at FLASH_REGS_ADDR (0x40022000)
+#define STM32L4_FLASH_KEYR (FLASH_REGS_ADDR + 0x08)
+#define STM32L4_FLASH_SR (FLASH_REGS_ADDR + 0x10)
+#define STM32L4_FLASH_CR (FLASH_REGS_ADDR + 0x14)
+#define STM32L4_FLASH_OPTR (FLASH_REGS_ADDR + 0x20)
+
+#define STM32L4_FLASH_SR_BSY 16
+#define STM32L4_FLASH_SR_ERRMASK 0x3f8 /* SR [9:3] */
+
+#define STM32L4_FLASH_CR_LOCK 31 /* Lock control register */
+#define STM32L4_FLASH_CR_PG 0 /* Program */
+#define STM32L4_FLASH_CR_PER 1 /* Page erase */
+#define STM32L4_FLASH_CR_MER1 2 /* Bank 1 erase */
+#define STM32L4_FLASH_CR_MER2 15 /* Bank 2 erase */
+#define STM32L4_FLASH_CR_STRT 16 /* Start command */
+#define STM32L4_FLASH_CR_BKER 11 /* Bank select for page erase */
+#define STM32L4_FLASH_CR_PNB 3 /* Page number (8 bits) */
+// Bits requesting flash operations (useful when we want to clear them)
+#define STM32L4_FLASH_CR_OPBITS \
+ ((1lu<<STM32L4_FLASH_CR_PG) | (1lu<<STM32L4_FLASH_CR_PER) \
+ | (1lu<<STM32L4_FLASH_CR_MER1) | (1lu<<STM32L4_FLASH_CR_MER1))
+// Page is fully specified by BKER and PNB
+#define STM32L4_FLASH_CR_PAGEMASK (0x1fflu << STM32L4_FLASH_CR_PNB)
+
+#define STM32L4_FLASH_OPTR_DUALBANK 21
+
+//STM32L0x flash register base and offsets
+//same as 32L1 above
+// RM0090 - DM00031020.pdf
+#define STM32L0_FLASH_REGS_ADDR ((uint32_t)0x40022000)
+#define FLASH_ACR_OFF ((uint32_t) 0x00)
+#define FLASH_PECR_OFF ((uint32_t) 0x04)
+#define FLASH_PDKEYR_OFF ((uint32_t) 0x08)
+#define FLASH_PEKEYR_OFF ((uint32_t) 0x0c)
+#define FLASH_PRGKEYR_OFF ((uint32_t) 0x10)
+#define FLASH_OPTKEYR_OFF ((uint32_t) 0x14)
+#define FLASH_SR_OFF ((uint32_t) 0x18)
+#define FLASH_OBR_OFF ((uint32_t) 0x1c)
+#define FLASH_WRPR_OFF ((uint32_t) 0x20)
+
+
//STM32F4
#define FLASH_F4_REGS_ADDR ((uint32_t)0x40023c00)
#define FLASH_F4_CR_LOCK 31
#define FLASH_F4_CR_SER 1
#define FLASH_F4_CR_SNB 3
-#define FLASH_F4_CR_SNB_MASK 0x38
+#define FLASH_F4_CR_SNB_MASK 0xf8
#define FLASH_F4_SR_BSY 16
+#define L1_WRITE_BLOCK_SIZE 0x80
+#define L0_WRITE_BLOCK_SIZE 0x40
void write_uint32(unsigned char* buf, uint32_t ui) {
if (!is_bigendian()) { // le -> le (don't swap)
static inline uint32_t read_flash_cr(stlink_t *sl) {
uint32_t res;
if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) ||(sl->chip_id == STM32_CHIPID_F4_DE) ||
- (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD))
+ (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) ||
+ (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7) || (sl->chip_id == STM32_CHIPID_F4_DSI))
res = stlink_read_debug32(sl, FLASH_F4_CR);
+ else if (sl->chip_id == STM32_CHIPID_L4)
+ res = stlink_read_debug32(sl, STM32L4_FLASH_CR);
else
res = stlink_read_debug32(sl, FLASH_CR);
#if DEBUG_FLASH
static inline unsigned int is_flash_locked(stlink_t *sl) {
/* return non zero for true */
+ uint32_t cr = read_flash_cr(sl);
+
if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) ||
- (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD))
- return read_flash_cr(sl) & (1 << FLASH_F4_CR_LOCK);
+ (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) ||
+ (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7) || (sl->chip_id == STM32_CHIPID_F4_DSI))
+ return cr & (1 << FLASH_F4_CR_LOCK);
+ else if (sl->chip_id == STM32_CHIPID_L4)
+ return cr & (1lu << STM32L4_FLASH_CR_LOCK);
else
- return read_flash_cr(sl) & (1 << FLASH_CR_LOCK);
+ return cr & (1 << FLASH_CR_LOCK);
}
static void unlock_flash(stlink_t *sl) {
the FPEC block until next reset.
*/
if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) ||
- (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD)) {
+ (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) ||
+ (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7) || (sl->chip_id == STM32_CHIPID_F4_DSI)) {
stlink_write_debug32(sl, FLASH_F4_KEYR, FLASH_KEY1);
stlink_write_debug32(sl, FLASH_F4_KEYR, FLASH_KEY2);
+ } else if (sl->chip_id == STM32_CHIPID_L4) {
+ stlink_write_debug32(sl, STM32L4_FLASH_KEYR, FLASH_KEY1);
+ stlink_write_debug32(sl, STM32L4_FLASH_KEYR, FLASH_KEY2);
} else {
stlink_write_debug32(sl, FLASH_KEYR, FLASH_KEY1);
stlink_write_debug32(sl, FLASH_KEYR, FLASH_KEY2);
static void lock_flash(stlink_t *sl) {
if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) ||
- (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD)) {
+ (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) ||
+ (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7) || (sl->chip_id == STM32_CHIPID_F4_DSI)) {
const uint32_t n = read_flash_cr(sl) | (1 << FLASH_F4_CR_LOCK);
stlink_write_debug32(sl, FLASH_F4_CR, n);
+ } else if (sl->chip_id == STM32_CHIPID_L4) {
+ const uint32_t n = read_flash_cr(sl) | (1lu << STM32L4_FLASH_CR_LOCK);
+ stlink_write_debug32(sl, STM32L4_FLASH_CR, n);
} else {
/* write to 1 only. reset by hw at unlock sequence */
const uint32_t n = read_flash_cr(sl) | (1 << FLASH_CR_LOCK);
static void set_flash_cr_pg(stlink_t *sl) {
if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) ||
- (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD)) {
+ (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) ||
+ (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7) || (sl->chip_id == STM32_CHIPID_F4_DSI)) {
uint32_t x = read_flash_cr(sl);
x |= (1 << FLASH_CR_PG);
stlink_write_debug32(sl, FLASH_F4_CR, x);
+ } else if (sl->chip_id == STM32_CHIPID_L4) {
+ uint32_t x = read_flash_cr(sl);
+ x &=~ STM32L4_FLASH_CR_OPBITS;
+ x |= (1 << STM32L4_FLASH_CR_PG);
+ stlink_write_debug32(sl, STM32L4_FLASH_CR, x);
} else {
const uint32_t n = 1 << FLASH_CR_PG;
stlink_write_debug32(sl, FLASH_CR, n);
static void __attribute__((unused)) clear_flash_cr_pg(stlink_t *sl) {
const uint32_t n = read_flash_cr(sl) & ~(1 << FLASH_CR_PG);
if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) ||
- (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD))
+ (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) ||
+ (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7) || (sl->chip_id == STM32_CHIPID_F4_DSI))
stlink_write_debug32(sl, FLASH_F4_CR, n);
else
stlink_write_debug32(sl, FLASH_CR, n);
static void set_flash_cr_mer(stlink_t *sl) {
if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) ||
- (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD))
+ (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) ||
+ (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7) || (sl->chip_id == STM32_CHIPID_F4_DSI))
stlink_write_debug32(sl, FLASH_F4_CR,
stlink_read_debug32(sl, FLASH_F4_CR) | (1 << FLASH_CR_MER));
- else
+ else if (sl->chip_id == STM32_CHIPID_L4) {
+ uint32_t x = stlink_read_debug32(sl, STM32L4_FLASH_CR);
+ x &=~ STM32L4_FLASH_CR_OPBITS;
+ x |= (1lu << STM32L4_FLASH_CR_MER1) | (1lu << STM32L4_FLASH_CR_MER2);
+ stlink_write_debug32(sl, STM32L4_FLASH_CR, x);
+ } else
stlink_write_debug32(sl, FLASH_CR,
stlink_read_debug32(sl, FLASH_CR) | (1 << FLASH_CR_MER));
}
static void __attribute__((unused)) clear_flash_cr_mer(stlink_t *sl) {
if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) ||
- (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD))
+ (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) ||
+ (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7) || (sl->chip_id == STM32_CHIPID_F4_DSI))
stlink_write_debug32(sl, FLASH_F4_CR,
stlink_read_debug32(sl, FLASH_F4_CR) & ~(1 << FLASH_CR_MER));
else
static void set_flash_cr_strt(stlink_t *sl) {
if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) ||
- (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD)) {
+ (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) ||
+ (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7) || (sl->chip_id == STM32_CHIPID_F4_DSI)) {
uint32_t x = read_flash_cr(sl);
x |= (1 << FLASH_F4_CR_STRT);
stlink_write_debug32(sl, FLASH_F4_CR, x);
+ } else if (sl->chip_id == STM32_CHIPID_L4) {
+ uint32_t x = read_flash_cr(sl);
+ x |= (1lu << STM32L4_FLASH_CR_STRT);
+ stlink_write_debug32(sl, STM32L4_FLASH_CR, x);
} else {
stlink_write_debug32(sl, FLASH_CR,
stlink_read_debug32(sl, FLASH_CR) | (1 << FLASH_CR_STRT) );
static inline uint32_t read_flash_sr(stlink_t *sl) {
uint32_t res;
if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) ||
- (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD))
+ (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) ||
+ (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7) || (sl->chip_id == STM32_CHIPID_F4_DSI))
res = stlink_read_debug32(sl, FLASH_F4_SR);
+ else if (sl->chip_id == STM32_CHIPID_L4)
+ res = stlink_read_debug32(sl, STM32L4_FLASH_SR);
else
res = stlink_read_debug32(sl, FLASH_SR);
//fprintf(stdout, "SR:0x%x\n", *(uint32_t*) sl->q_buf);
static inline unsigned int is_flash_busy(stlink_t *sl) {
if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) ||
- (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD))
+ (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) ||
+ (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7) || (sl->chip_id == STM32_CHIPID_F4_DSI))
return read_flash_sr(sl) & (1 << FLASH_F4_SR_BSY);
+ else if (sl->chip_id == STM32_CHIPID_L4)
+ return read_flash_sr(sl) & (1 << STM32L4_FLASH_SR_BSY);
else
return read_flash_sr(sl) & (1 << FLASH_SR_BSY);
}
stlink_write_debug32(sl, FLASH_F4_CR, x);
}
+static inline void write_flash_cr_bker_pnb(stlink_t *sl, uint32_t n) {
+ uint32_t x = read_flash_cr(sl);
+ x &=~ STM32L4_FLASH_CR_OPBITS;
+ x &=~ STM32L4_FLASH_CR_PAGEMASK;
+ x |= (n << STM32L4_FLASH_CR_PNB);
+ x |= (1lu << STM32L4_FLASH_CR_PER);
+#if DEBUG_FLASH
+ fprintf(stdout, "BKER:PNB:0x%x 0x%x\n", x, n);
+#endif
+ stlink_write_debug32(sl, STM32L4_FLASH_CR, x);
+}
+
// Delegates to the backends...
void stlink_close(stlink_t *sl) {
if ((sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS) && ( flash_size == 0 )) {
sl->flash_size = 128 * 1024;
+ } else if (sl->chip_id == STM32_CHIPID_L1_CAT2) {
+ sl->flash_size = (flash_size & 0xff) * 1024;
} else if ((sl->chip_id & 0xFFF) == STM32_CHIPID_L1_HIGH) {
// 0 is 384k and 1 is 256k
if ( flash_size == 0 ) {
sl->sys_base = params->bootrom_base;
sl->sys_size = params->bootrom_size;
+ //medium and low devices have the same chipid. ram size depends on flash size.
+ //STM32F100xx datasheet Doc ID 16455 Table 2
+ if(sl->chip_id == STM32_CHIPID_F1_VL_MEDIUM_LOW && sl->flash_size < 64 * 1024){
+ sl->sram_size = 0x1000;
+ }
+
ILOG("Device connected is: %s, id %#x\n", params->description, chip_id);
// TODO make note of variable page size here.....
ILOG("SRAM size: %#x bytes (%d KiB), Flash: %#x bytes (%d KiB) in pages of %zd bytes\n",
int error = -1;
size_t off;
+ size_t len;
mapped_file_t mf = MAPPED_FILE_INITIALIZER;
} else if ((addr + mf.len) > (sl->sram_base + sl->sram_size)) {
fprintf(stderr, "addr too high\n");
goto on_error;
- } else if ((addr & 3) || (mf.len & 3)) {
+ } else if (addr & 3) {
/* todo */
- fprintf(stderr, "unaligned addr or size\n");
+ fprintf(stderr, "unaligned addr\n");
goto on_error;
}
+
+ len = mf.len;
+
+ if(len & 3) {
+ len -= len & 3;
+ }
+
/* do the copy by 1k blocks */
- for (off = 0; off < mf.len; off += 1024) {
+ for (off = 0; off < len; off += 1024) {
size_t size = 1024;
- if ((off + size) > mf.len)
- size = mf.len - off;
+ if ((off + size) > len)
+ size = len - off;
memcpy(sl->q_buf, mf.base + off, size);
stlink_write_mem32(sl, addr + off, size);
}
+ if(mf.len > len) {
+ memcpy(sl->q_buf, mf.base + len, mf.len - len);
+ stlink_write_mem8(sl, addr + len, mf.len - len);
+ }
+
/* check the file ha been written */
if (check_file(sl, &mf, addr) == -1) {
fprintf(stderr, "check_file() == -1\n");
int error = -1;
size_t off;
int num_empty = 0;
- unsigned char erased_pattern = (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS
- || sl->chip_id == STM32_CHIPID_L1_HIGH || sl->chip_id == STM32_CHIPID_L152_RE) ? 0:0xff;
+ unsigned char erased_pattern = (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_CAT2
+ || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS || sl->chip_id == STM32_CHIPID_L1_HIGH
+ || sl->chip_id == STM32_CHIPID_L152_RE) ? 0:0xff;
const int fd = open(path, O_RDWR | O_TRUNC | O_CREAT, 00700);
if (fd == -1) {
}
uint32_t calculate_F4_sectornum(uint32_t flashaddr){
+ uint32_t offset = 0;
flashaddr &= ~STM32_FLASH_BASE; //Page now holding the actual flash address
- if (flashaddr<0x4000) return (0);
- else if(flashaddr<0x8000) return(1);
- else if(flashaddr<0xc000) return(2);
- else if(flashaddr<0x10000) return(3);
- else if(flashaddr<0x20000) return(4);
- else return(flashaddr/0x20000)+4;
+ if (flashaddr >= 0x100000) {
+ offset = 12;
+ flashaddr -= 0x100000;
+ }
+ if (flashaddr<0x4000) return (offset + 0);
+ else if(flashaddr<0x8000) return(offset + 1);
+ else if(flashaddr<0xc000) return(offset + 2);
+ else if(flashaddr<0x10000) return(offset + 3);
+ else if(flashaddr<0x20000) return(offset + 4);
+ else return offset + (flashaddr/0x20000) +4;
}
+uint32_t calculate_F7_sectornum(uint32_t flashaddr){
+ flashaddr &= ~STM32_FLASH_BASE; //Page now holding the actual flash address
+ if(flashaddr<0x20000) return(flashaddr/0x8000);
+ else if(flashaddr<0x40000) return(4);
+ else return(flashaddr/0x40000) +4;
+
+}
+
+// Returns BKER:PNB for the given page address
+uint32_t calculate_L4_page(stlink_t *sl, uint32_t flashaddr) {
+ uint32_t bker = 0;
+ uint32_t flashopt = stlink_read_debug32(sl, STM32L4_FLASH_OPTR);
+ flashaddr -= STM32_FLASH_BASE;
+ if (flashopt & (1lu << STM32L4_FLASH_OPTR_DUALBANK)) {
+ uint32_t banksize = sl->flash_size / 2;
+ if (flashaddr > banksize) {
+ flashaddr -= banksize;
+ bker = 0x100;
+ }
+ }
+ // For 1MB chips without the dual-bank option set, the page address will
+ // overflow into the BKER bit, which gives us the correct bank:page value.
+ return bker | flashaddr/sl->flash_pgsz;
+}
+
uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr){
if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) ||
- (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD)) {
+ (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) ||
+ (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F4_DSI)) {
uint32_t sector=calculate_F4_sectornum(flashaddr);
+ if (sector>= 12) {
+ sector -= 12;
+ }
if (sector<4) sl->flash_pgsz=0x4000;
else if(sector<5) sl->flash_pgsz=0x10000;
else sl->flash_pgsz=0x20000;
}
+ else if (sl->chip_id == STM32_CHIPID_F7) {
+ uint32_t sector=calculate_F7_sectornum(flashaddr);
+ if (sector<4) sl->flash_pgsz=0x8000;
+ else if(sector<5) sl->flash_pgsz=0x20000;
+ else sl->flash_pgsz=0x40000;
+ }
return (sl->flash_pgsz);
}
int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr)
{
if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) ||
- (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD)) {
+ (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) ||
+ (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7) || (sl->chip_id == STM32_CHIPID_L4)|| (sl->chip_id == STM32_CHIPID_F4_DSI)) {
/* wait for ongoing op to finish */
wait_flash_busy(sl);
unlock_flash_if(sl);
/* select the page to erase */
- // calculate the actual page from the address
- uint32_t sector=calculate_F4_sectornum(flashaddr);
+ if (sl->chip_id == STM32_CHIPID_L4) {
+ // calculate the actual bank+page from the address
+ uint32_t page = calculate_L4_page(sl, flashaddr);
+
+ write_flash_cr_bker_pnb(sl, page);
+ } else if (sl->chip_id == STM32_CHIPID_F7) {
+ // calculate the actual page from the address
+ uint32_t sector=calculate_F7_sectornum(flashaddr);
- fprintf(stderr, "EraseFlash - Sector:0x%x Size:0x%x\n", sector, stlink_calculate_pagesize(sl, flashaddr));
- write_flash_cr_snb(sl, sector);
+ fprintf(stderr, "EraseFlash - Sector:0x%x Size:0x%x\n", sector, stlink_calculate_pagesize(sl, flashaddr));
+
+ write_flash_cr_snb(sl, sector);
+ } else {
+ // calculate the actual page from the address
+ uint32_t sector=calculate_F4_sectornum(flashaddr);
+
+ fprintf(stderr, "EraseFlash - Sector:0x%x Size:0x%x\n", sector, stlink_calculate_pagesize(sl, flashaddr));
+
+ //the SNB values for flash sectors in the second bank do not directly follow the values for the first bank on 2mb devices...
+ if (sector >= 12) sector += 4;
+
+ write_flash_cr_snb(sl, sector);
+ }
/* start erase operation */
set_flash_cr_strt(sl);
#if DEBUG_FLASH
fprintf(stdout, "Erase Final CR:0x%x\n", read_flash_cr(sl));
#endif
- } else if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS
- || sl->chip_id == STM32_CHIPID_L1_HIGH || sl->chip_id == STM32_CHIPID_L152_RE) {
+ } else if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_CAT2
+ || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS || sl->chip_id == STM32_CHIPID_L1_HIGH
+ || sl->chip_id == STM32_CHIPID_L152_RE || sl->chip_id == STM32_CHIPID_L0) {
uint32_t val;
+ uint32_t flash_regs_base;
+ if (sl->chip_id == STM32_CHIPID_L0) {
+ flash_regs_base = STM32L0_FLASH_REGS_ADDR;
+ } else {
+ flash_regs_base = STM32L_FLASH_REGS_ADDR;
+ }
/* check if the locks are set */
- val = stlink_read_debug32(sl, STM32L_FLASH_PECR);
+ val = stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF);
if((val & (1<<0))||(val & (1<<1))) {
/* disable pecr protection */
- stlink_write_debug32(sl, STM32L_FLASH_PEKEYR, 0x89abcdef);
- stlink_write_debug32(sl, STM32L_FLASH_PEKEYR, 0x02030405);
+ stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, 0x89abcdef);
+ stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, 0x02030405);
/* check pecr.pelock is cleared */
- val = stlink_read_debug32(sl, STM32L_FLASH_PECR);
+ val = stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF);
if (val & (1 << 0)) {
WLOG("pecr.pelock not clear (%#x)\n", val);
return -1;
}
/* unlock program memory */
- stlink_write_debug32(sl, STM32L_FLASH_PRGKEYR, 0x8c9daebf);
- stlink_write_debug32(sl, STM32L_FLASH_PRGKEYR, 0x13141516);
+ stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, 0x8c9daebf);
+ stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, 0x13141516);
/* check pecr.prglock is cleared */
- val = stlink_read_debug32(sl, STM32L_FLASH_PECR);
+ val = stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF);
if (val & (1 << 1)) {
WLOG("pecr.prglock not clear (%#x)\n", val);
return -1;
/* set pecr.{erase,prog} */
val |= (1 << 9) | (1 << 3);
- stlink_write_debug32(sl, STM32L_FLASH_PECR, val);
-
+ stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val);
#if 0 /* fix_to_be_confirmed */
/* wait for sr.busy to be cleared
page erase command, even though PM0062 recommends to wait before it.
Test shows that a few iterations is performed in the following loop
before busy bit is cleared.*/
- while ((stlink_read_debug32(sl, STM32L_FLASH_SR) & (1 << 0)) != 0)
+ while ((stlink_read_debug32(sl, flash_regs_base + FLASH_SR_OFF) & (1 << 0)) != 0)
;
/* reset lock bits */
- val = stlink_read_debug32(sl, STM32L_FLASH_PECR)
+ val = stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF)
| (1 << 0) | (1 << 1) | (1 << 2);
- stlink_write_debug32(sl, STM32L_FLASH_PECR, val);
+ stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val);
} else if (sl->core_id == STM32VL_CORE_ID
|| sl->core_id == STM32F0_CORE_ID
|| sl->chip_id == STM32_CHIPID_F3
- || sl->chip_id == STM32_CHIPID_F37x) {
+ || sl->chip_id == STM32_CHIPID_F3_SMALL
+ || sl->chip_id == STM32_CHIPID_F303_HIGH
+ || sl->chip_id == STM32_CHIPID_F37x
+ || sl->chip_id == STM32_CHIPID_F334) {
/* wait for ongoing op to finish */
wait_flash_busy(sl);
}
int stlink_erase_flash_mass(stlink_t *sl) {
- if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS
- || sl->chip_id == STM32_CHIPID_L1_HIGH || sl->chip_id == STM32_CHIPID_L152_RE) {
+ if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_CAT2
+ || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS || sl->chip_id == STM32_CHIPID_L1_HIGH
+ || sl->chip_id == STM32_CHIPID_L152_RE || sl->chip_id == STM32_CHIPID_L0) {
/* erase each page */
int i = 0, num_pages = sl->flash_size/sl->flash_pgsz;
for (i = 0; i < num_pages; i++) {
0x00, 0xbe
};
+ static const uint8_t loader_code_stm32l0[] = {
+
+ /*
+ r0, input, dest addr
+ r1, input, source addr
+ r2, input, word count
+ r3, output, word count
+ */
+
+ 0x00, 0x23,
+ 0x04, 0xe0,
+
+ 0x0c, 0x68,
+ 0x04, 0x60,
+ 0x01, 0x33,
+ 0x04, 0x31,
+ 0x04, 0x30,
+
+ 0x93, 0x42,
+ 0xf8, 0xd3,
+ 0x00, 0xbe
+ };
+
static const uint8_t loader_code_stm32f4[] = {
// flashloaders/stm32f4.s
0x00, 0x3c, 0x02, 0x40,
};
+ static const uint8_t loader_code_stm32f4_lv[] = {
+ // flashloaders/stm32f4lv.s
+ 0x92, 0x00,
+
+ 0x08, 0x4b,
+ 0x62, 0xb1,
+ 0x04, 0x78,
+ 0x0c, 0x70,
+
+ 0xdc, 0x89,
+ 0x14, 0xf0, 0x01, 0x0f,
+ 0xfb, 0xd1,
+ 0x00, 0xf1, 0x01, 0x00,
+ 0x01, 0xf1, 0x01, 0x01,
+ 0xa2, 0xf1, 0x01, 0x02,
+ 0xf1, 0xe7,
+
+ 0x00, 0xbe,
+ 0x00, 0xbf,
+
+ 0x00, 0x3c, 0x02, 0x40,
+ };
+
+ static const uint8_t loader_code_stm32l4[] = {
+ // flashloaders/stm32l4.s
+ 0x08, 0x4b, // start: ldr r3, [pc, #32] ; <flash_base>
+ 0x72, 0xb1, // next: cbz r2, <done>
+ 0x04, 0x68, // ldr r4, [r0, #0]
+ 0x45, 0x68, // ldr r5, [r0, #4]
+ 0x0c, 0x60, // str r4, [r1, #0]
+ 0x4d, 0x60, // str r5, [r1, #4]
+ 0x5c, 0x8a, // wait: ldrh r4, [r3, #18]
+ 0x14, 0xf0, 0x01, 0x0f, // tst.w r4, #1
+ 0xfb, 0xd1, // bne.n <wait>
+ 0x00, 0xf1, 0x08, 0x00, // add.w r0, r0, #8
+ 0x01, 0xf1, 0x08, 0x01, // add.w r1, r1, #8
+ 0xa2, 0xf1, 0x02, 0x02, // add.w r2, r2, #2
+ 0xef, 0xe7, // b.n <next>
+ 0x00, 0xbe, // done: bkpt 0x0000
+ 0x00, 0x20, 0x02, 0x40 // flash_base: .word 0x40022000
+ };
+
+ static const uint8_t loader_code_stm32f7[] = {
+ 0x08, 0x4b,
+ 0x72, 0xb1,
+ 0x04, 0x68,
+ 0x0c, 0x60,
+ 0xbf, 0xf3, 0x4f, 0x8f, // DSB Memory barrier for in order flash write
+ 0xdc, 0x89,
+ 0x14, 0xf0, 0x01, 0x0f,
+ 0xfb, 0xd1,
+ 0x00, 0xf1, 0x04, 0x00,
+ 0x01, 0xf1, 0x04, 0x01,
+ 0xa2, 0xf1, 0x01, 0x02,
+ 0xef, 0xe7,
+ 0x00, 0xbe, // bkpt #0x00
+ 0x00, 0x3c, 0x02, 0x40,
+ };
+
const uint8_t* loader_code;
size_t loader_size;
- if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS
- || sl->chip_id == STM32_CHIPID_L1_HIGH || sl->chip_id == STM32_CHIPID_L152_RE ) { /* stm32l */
+ if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_CAT2
+ || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS || sl->chip_id == STM32_CHIPID_L1_HIGH
+ || sl->chip_id == STM32_CHIPID_L152_RE) { /* stm32l */
loader_code = loader_code_stm32l;
loader_size = sizeof(loader_code_stm32l);
- } else if (sl->core_id == STM32VL_CORE_ID || sl->chip_id == STM32_CHIPID_F3 || sl->chip_id == STM32_CHIPID_F37x) {
+ } else if (sl->core_id == STM32VL_CORE_ID
+ || sl->chip_id == STM32_CHIPID_F3
+ || sl->chip_id == STM32_CHIPID_F3_SMALL
+ || sl->chip_id == STM32_CHIPID_F303_HIGH
+ || sl->chip_id == STM32_CHIPID_F37x
+ || sl->chip_id == STM32_CHIPID_F334) {
loader_code = loader_code_stm32vl;
loader_size = sizeof(loader_code_stm32vl);
} else if (sl->chip_id == STM32_CHIPID_F2 || sl->chip_id == STM32_CHIPID_F4 || (sl->chip_id == STM32_CHIPID_F4_DE) ||
- sl->chip_id == STM32_CHIPID_F4_LP || sl->chip_id == STM32_CHIPID_F4_HD){
- loader_code = loader_code_stm32f4;
- loader_size = sizeof(loader_code_stm32f4);
- } else if (sl->chip_id == STM32_CHIPID_F0 || sl->chip_id == STM32_CHIPID_F0_CAN || sl->chip_id == STM32_CHIPID_F0_SMALL) {
+ sl->chip_id == STM32_CHIPID_F4_LP || sl->chip_id == STM32_CHIPID_F4_HD || (sl->chip_id == STM32_CHIPID_F411RE) ||
+ (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F4_DSI)){
+ int voltage = stlink_target_voltage(sl);
+ if (voltage > 2700) {
+ loader_code = loader_code_stm32f4;
+ loader_size = sizeof(loader_code_stm32f4);
+ } else {
+ loader_code = loader_code_stm32f4_lv;
+ loader_size = sizeof(loader_code_stm32f4_lv);
+ }
+ } else if (sl->chip_id == STM32_CHIPID_F7){
+ loader_code = loader_code_stm32f7;
+ loader_size = sizeof(loader_code_stm32f7);
+ } else if (sl->chip_id == STM32_CHIPID_F0 || sl->chip_id == STM32_CHIPID_F04 || sl->chip_id == STM32_CHIPID_F0_CAN || sl->chip_id == STM32_CHIPID_F0_SMALL || sl->chip_id == STM32_CHIPID_F09X) {
loader_code = loader_code_stm32f0;
loader_size = sizeof(loader_code_stm32f0);
+ } else if (sl->chip_id == STM32_CHIPID_L0) {
+ loader_code = loader_code_stm32l0;
+ loader_size = sizeof(loader_code_stm32l0);
+ } else if (sl->chip_id == STM32_CHIPID_L4) {
+ loader_code = loader_code_stm32l4;
+ loader_size = sizeof(loader_code_stm32l4);
} else {
ELOG("unknown coreid, not sure what flash loader to use, aborting!: %x\n", sl->core_id);
return -1;
}
-int stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned num_half_pages)
+int stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t len, uint32_t pagesize)
{
unsigned int count;
+ unsigned int num_half_pages = len / pagesize;
uint32_t val;
+ uint32_t flash_regs_base;
flash_loader_t fl;
+ if (sl->chip_id == STM32_CHIPID_L0) {
+ flash_regs_base = STM32L0_FLASH_REGS_ADDR;
+ } else {
+ flash_regs_base = STM32L_FLASH_REGS_ADDR;
+ }
+
ILOG("Starting Half page flash write for STM32L core id\n");
/* flash loader initialization */
if (init_flash_loader(sl, &fl) == -1) {
return -1;
}
/* Unlock already done */
- val = stlink_read_debug32(sl, STM32L_FLASH_PECR);
+ val = stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF);
val |= (1 << FLASH_L1_FPRG);
- stlink_write_debug32(sl, STM32L_FLASH_PECR, val);
+ stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val);
val |= (1 << FLASH_L1_PROG);
- stlink_write_debug32(sl, STM32L_FLASH_PECR, val);
- while ((stlink_read_debug32(sl, STM32L_FLASH_SR) & (1 << 0)) != 0) {}
+ stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val);
+ while ((stlink_read_debug32(sl, flash_regs_base + FLASH_SR_OFF) & (1 << 0)) != 0) {}
-#define L1_WRITE_BLOCK_SIZE 0x80
for (count = 0; count < num_half_pages; count ++) {
- if (run_flash_loader(sl, &fl, addr + count * L1_WRITE_BLOCK_SIZE, base + count * L1_WRITE_BLOCK_SIZE, L1_WRITE_BLOCK_SIZE) == -1) {
- WLOG("l1_run_flash_loader(%#zx) failed! == -1\n", addr + count * L1_WRITE_BLOCK_SIZE);
- val = stlink_read_debug32(sl, STM32L_FLASH_PECR);
+ if (run_flash_loader(sl, &fl, addr + count * pagesize, base + count * pagesize, pagesize) == -1) {
+ WLOG("l1_run_flash_loader(%#zx) failed! == -1\n", addr + count * pagesize);
+ val = stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF);
val &= ~((1 << FLASH_L1_FPRG) |(1 << FLASH_L1_PROG));
- stlink_write_debug32(sl, STM32L_FLASH_PECR, val);
+ stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val);
return -1;
}
/* wait for sr.busy to be cleared */
fprintf(stdout, "\r%3u/%u halfpages written", count + 1, num_half_pages);
fflush(stdout);
}
- while ((stlink_read_debug32(sl, STM32L_FLASH_SR) & (1 << 0)) != 0) {
+ while ((stlink_read_debug32(sl, flash_regs_base + FLASH_SR_OFF) & (1 << 0)) != 0) {
}
}
- val = stlink_read_debug32(sl, STM32L_FLASH_PECR);
+ val = stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF);
val &= ~(1 << FLASH_L1_PROG);
- stlink_write_debug32(sl, STM32L_FLASH_PECR, val);
- val = stlink_read_debug32(sl, STM32L_FLASH_PECR);
+ stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val);
+ val = stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF);
val &= ~(1 << FLASH_L1_FPRG);
- stlink_write_debug32(sl, STM32L_FLASH_PECR, val);
+ stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val);
return 0;
}
ILOG("Finished erasing %d pages of %d (%#x) bytes\n",
page_count, sl->flash_pgsz, sl->flash_pgsz);
- if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) ||
- (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD)) {
+ if ((sl->chip_id == STM32_CHIPID_F2) ||
+ (sl->chip_id == STM32_CHIPID_F4) ||
+ (sl->chip_id == STM32_CHIPID_F4_DE) ||
+ (sl->chip_id == STM32_CHIPID_F4_LP) ||
+ (sl->chip_id == STM32_CHIPID_F4_HD) ||
+ (sl->chip_id == STM32_CHIPID_F411RE) ||
+ (sl->chip_id == STM32_CHIPID_F446) ||
+ (sl->chip_id == STM32_CHIPID_F7) ||
+ (sl->chip_id == STM32_CHIPID_L4) ||
+ (sl->chip_id == STM32_CHIPID_F4_DSI)) {
/* todo: check write operation */
- ILOG("Starting Flash write for F2/F4\n");
+ ILOG("Starting Flash write for F2/F4/L4\n");
/* flash loader initialization */
if (init_flash_loader(sl, &fl) == -1) {
ELOG("init_flash_loader() == -1\n");
unlock_flash_if(sl);
/* TODO: Check that Voltage range is 2.7 - 3.6 V */
- /* set parallelisim to 32 bit*/
- write_flash_cr_psiz(sl, 2);
+ if (sl->chip_id != STM32_CHIPID_L4) {
+ /* set parallelisim to 32 bit*/
+ int voltage = stlink_target_voltage(sl);
+ if (voltage > 2700) {
+ printf("enabling 32-bit flash writes\n");
+ write_flash_cr_psiz(sl, 2);
+ } else {
+ printf("Target voltage (%d mV) too low for 32-bit flash, using 8-bit flash writes\n", voltage);
+ write_flash_cr_psiz(sl, 0);
+ }
+ } else {
+ /* L4 does not have a byte-write mode */
+ int voltage = stlink_target_voltage(sl);
+ if (voltage < 1710) {
+ printf("Target voltage (%d mV) too low for flash writes!\n", voltage);
+ return -1;
+ }
+ }
/* set programming mode */
set_flash_cr_pg(sl);
} //STM32F4END
- else if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS
- || sl->chip_id == STM32_CHIPID_L1_HIGH || sl->chip_id == STM32_CHIPID_L152_RE ) {
+ else if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_CAT2
+ || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS || sl->chip_id == STM32_CHIPID_L1_HIGH
+ || sl->chip_id == STM32_CHIPID_L152_RE || sl->chip_id == STM32_CHIPID_L0) {
/* use fast word write. todo: half page. */
uint32_t val;
+ uint32_t flash_regs_base;
+ uint32_t pagesize;
+
+ if (sl->chip_id == STM32_CHIPID_L0) {
+ flash_regs_base = STM32L0_FLASH_REGS_ADDR;
+ pagesize = L0_WRITE_BLOCK_SIZE;
+ } else {
+ flash_regs_base = STM32L_FLASH_REGS_ADDR;
+ pagesize = L1_WRITE_BLOCK_SIZE;
+ }
/* todo: check write operation */
/* disable pecr protection */
- stlink_write_debug32(sl, STM32L_FLASH_PEKEYR, 0x89abcdef);
- stlink_write_debug32(sl, STM32L_FLASH_PEKEYR, 0x02030405);
+ stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, 0x89abcdef);
+ stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, 0x02030405);
/* check pecr.pelock is cleared */
- val = stlink_read_debug32(sl, STM32L_FLASH_PECR);
+ val = stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF);
if (val & (1 << 0)) {
fprintf(stderr, "pecr.pelock not clear\n");
return -1;
}
/* unlock program memory */
- stlink_write_debug32(sl, STM32L_FLASH_PRGKEYR, 0x8c9daebf);
- stlink_write_debug32(sl, STM32L_FLASH_PRGKEYR, 0x13141516);
+ stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, 0x8c9daebf);
+ stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, 0x13141516);
/* check pecr.prglock is cleared */
- val = stlink_read_debug32(sl, STM32L_FLASH_PECR);
+ val = stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF);
if (val & (1 << 1)) {
fprintf(stderr, "pecr.prglock not clear\n");
return -1;
}
off = 0;
- if (len > L1_WRITE_BLOCK_SIZE) {
- if (stm32l1_write_half_pages(sl, addr, base, len/L1_WRITE_BLOCK_SIZE) == -1) {
+ if (len > pagesize) {
+ if (stm32l1_write_half_pages(sl, addr, base, len, pagesize) == -1) {
/* This may happen on a blank device! */
WLOG("\nwrite_half_pages failed == -1\n");
} else {
- off = (len /L1_WRITE_BLOCK_SIZE)*L1_WRITE_BLOCK_SIZE;
+ off = (len / pagesize)*pagesize;
}
}
stlink_write_debug32(sl, addr + off, data);
/* wait for sr.busy to be cleared */
- while ((stlink_read_debug32(sl, STM32L_FLASH_SR) & (1 << 0)) != 0)
+ while ((stlink_read_debug32(sl, flash_regs_base + FLASH_SR_OFF) & (1 << 0)) != 0)
;
/* todo: check redo write operation */
}
fprintf(stdout, "\n");
/* reset lock bits */
- val = stlink_read_debug32(sl, STM32L_FLASH_PECR)
+ val = stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF)
| (1 << 0) | (1 << 1) | (1 << 2);
- stlink_write_debug32(sl, STM32L_FLASH_PECR, val);
- } else if (sl->core_id == STM32VL_CORE_ID || sl->core_id == STM32F0_CORE_ID || sl->chip_id == STM32_CHIPID_F3 || sl->chip_id == STM32_CHIPID_F37x) {
- ILOG("Starting Flash write for VL/F0 core id\n");
+ stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val);
+ } else if (sl->core_id == STM32VL_CORE_ID ||
+ sl->core_id == STM32F0_CORE_ID ||
+ sl->chip_id == STM32_CHIPID_F3 ||
+ sl->chip_id == STM32_CHIPID_F3_SMALL ||
+ sl->chip_id == STM32_CHIPID_F303_HIGH ||
+ sl->chip_id == STM32_CHIPID_F334 ||
+ sl->chip_id == STM32_CHIPID_F37x) {
+ ILOG("Starting Flash write for VL/F0/F3 core id\n");
/* flash loader initialization */
if (init_flash_loader(sl, &fl) == -1) {
ELOG("init_flash_loader() == -1\n");
/* write the file in flash at addr */
int err;
unsigned int num_empty = 0, index;
- unsigned char erased_pattern =(sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS
- || sl->chip_id == STM32_CHIPID_L1_HIGH || sl->chip_id == STM32_CHIPID_L152_RE )?0:0xff;
+ unsigned char erased_pattern = (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_CAT2
+ || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS || sl->chip_id == STM32_CHIPID_L1_HIGH
+ || sl->chip_id == STM32_CHIPID_L152_RE) ? 0:0xff;
mapped_file_t mf = MAPPED_FILE_INITIALIZER;
if (map_file(&mf, path) == -1) {
ELOG("map_file() == -1\n");
return -1;
}
- if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS
- || sl->chip_id == STM32_CHIPID_L1_HIGH || sl->chip_id == STM32_CHIPID_L152_RE ) {
+ if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_CAT2
+ || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS || sl->chip_id == STM32_CHIPID_L1_HIGH
+ || sl->chip_id == STM32_CHIPID_L152_RE || sl->chip_id == STM32_CHIPID_L0) {
size_t count = size / sizeof(uint32_t);
if (size % sizeof(uint32_t)) ++count;
stlink_write_reg(sl, count, 2); /* count (32 bits words) */
stlink_write_reg(sl, fl->loader_addr, 15); /* pc register */
- } else if (sl->core_id == STM32VL_CORE_ID || sl->core_id == STM32F0_CORE_ID || sl->chip_id == STM32_CHIPID_F3 || sl->chip_id == STM32_CHIPID_F37x) {
+ } else if (sl->core_id == STM32VL_CORE_ID ||
+ sl->core_id == STM32F0_CORE_ID ||
+ sl->chip_id == STM32_CHIPID_F3 ||
+ sl->chip_id == STM32_CHIPID_F3_SMALL ||
+ sl->chip_id == STM32_CHIPID_F303_HIGH ||
+ sl->chip_id == STM32_CHIPID_F37x ||
+ sl->chip_id == STM32_CHIPID_F334) {
size_t count = size / sizeof(uint16_t);
if (size % sizeof(uint16_t)) ++count;
stlink_write_reg(sl, fl->loader_addr, 15); /* pc register */
} else if (sl->chip_id == STM32_CHIPID_F2 || sl->chip_id == STM32_CHIPID_F4 || (sl->chip_id == STM32_CHIPID_F4_DE) ||
- sl->chip_id == STM32_CHIPID_F4_LP || sl->chip_id == STM32_CHIPID_F4_HD) {
+ sl->chip_id == STM32_CHIPID_F4_LP || sl->chip_id == STM32_CHIPID_F4_HD || (sl->chip_id == STM32_CHIPID_F411RE) ||
+ (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7) || (sl->chip_id == STM32_CHIPID_L4) || (sl->chip_id == STM32_CHIPID_F4_DSI)) {
size_t count = size / sizeof(uint32_t);
if (size % sizeof(uint32_t)) ++count;
+ if (sl->chip_id == STM32_CHIPID_L4) {
+ if (count % 2) ++count;
+ }
/* setup core */
stlink_write_reg(sl, fl->buf_addr, 0); /* source */
}
/* check written byte count */
- if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS
- || sl->chip_id == STM32_CHIPID_L1_HIGH || sl->chip_id == STM32_CHIPID_L152_RE ) {
+ if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_CAT2
+ || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS || sl->chip_id == STM32_CHIPID_L1_HIGH
+ || sl->chip_id == STM32_CHIPID_L152_RE || sl->chip_id == STM32_CHIPID_L0) {
size_t count = size / sizeof(uint32_t);
if (size % sizeof(uint32_t)) ++count;
return -1;
}
- } else if (sl->core_id == STM32VL_CORE_ID || sl->core_id == STM32F0_CORE_ID || sl->chip_id == STM32_CHIPID_F3 || sl->chip_id == STM32_CHIPID_F37x) {
+ } else if (sl->core_id == STM32VL_CORE_ID ||
+ sl->core_id == STM32F0_CORE_ID ||
+ sl->chip_id == STM32_CHIPID_F3 ||
+ sl->chip_id == STM32_CHIPID_F3_SMALL ||
+ sl->chip_id == STM32_CHIPID_F303_HIGH ||
+ sl->chip_id == STM32_CHIPID_F37x ||
+ sl->chip_id == STM32_CHIPID_F334) {
stlink_read_reg(sl, 2, &rr);
if (rr.r[2] != 0) {
}
} else if (sl->chip_id == STM32_CHIPID_F2 || sl->chip_id == STM32_CHIPID_F4 || (sl->chip_id == STM32_CHIPID_F4_DE) ||
- sl->chip_id == STM32_CHIPID_F4_LP || sl->chip_id == STM32_CHIPID_F4_HD) {
+ sl->chip_id == STM32_CHIPID_F4_LP || sl->chip_id == STM32_CHIPID_F4_HD || (sl->chip_id == STM32_CHIPID_F411RE) ||
+ (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7) || (sl->chip_id == STM32_CHIPID_L4) ||
+ (sl->chip_id == STM32_CHIPID_F4_DSI)) {
stlink_read_reg(sl, 2, &rr);
if (rr.r[2] != 0) {