static inline uint32_t read_flash_cr(stlink_t *sl) {
uint32_t res;
- if(sl->chip_id==STM32F4_CHIP_ID)
+ if((sl->chip_id==STM32_CHIPID_F2) ||(sl->chip_id==STM32_CHIPID_F4))
res = stlink_read_debug32(sl, FLASH_F4_CR);
else
res = stlink_read_debug32(sl, FLASH_CR);
static inline unsigned int is_flash_locked(stlink_t *sl) {
/* return non zero for true */
- if(sl->chip_id==STM32F4_CHIP_ID)
+ if((sl->chip_id == STM32_CHIPID_F2) ||(sl->chip_id == STM32_CHIPID_F4))
return read_flash_cr(sl) & (1 << FLASH_F4_CR_LOCK);
else
return read_flash_cr(sl) & (1 << FLASH_CR_LOCK);
an invalid sequence results in a definitive lock of
the FPEC block until next reset.
*/
- if(sl->chip_id==STM32F4_CHIP_ID) {
+ if((sl->chip_id == STM32_CHIPID_F2) ||(sl->chip_id == STM32_CHIPID_F4)) {
stlink_write_debug32(sl, FLASH_F4_KEYR, FLASH_KEY1);
stlink_write_debug32(sl, FLASH_F4_KEYR, FLASH_KEY2);
}
}
static void lock_flash(stlink_t *sl) {
- if(sl->chip_id==STM32F4_CHIP_ID) {
+ if((sl->chip_id == STM32_CHIPID_F2) ||(sl->chip_id == STM32_CHIPID_F4)) {
const uint32_t n = read_flash_cr(sl) | (1 << FLASH_F4_CR_LOCK);
stlink_write_debug32(sl, FLASH_F4_CR, n);
}
static void set_flash_cr_pg(stlink_t *sl) {
- if(sl->chip_id==STM32F4_CHIP_ID) {
+ if((sl->chip_id == STM32_CHIPID_F2) ||(sl->chip_id == STM32_CHIPID_F4)) {
uint32_t x = read_flash_cr(sl);
x |= (1 << FLASH_CR_PG);
stlink_write_debug32(sl, FLASH_F4_CR, x);
static void __attribute__((unused)) clear_flash_cr_pg(stlink_t *sl) {
const uint32_t n = read_flash_cr(sl) & ~(1 << FLASH_CR_PG);
- if(sl->chip_id==STM32F4_CHIP_ID)
+ if((sl->chip_id == STM32_CHIPID_F2) ||(sl->chip_id == STM32_CHIPID_F4))
stlink_write_debug32(sl, FLASH_F4_CR, n);
else
stlink_write_debug32(sl, FLASH_CR, n);
}
static void set_flash_cr_mer(stlink_t *sl) {
- if(sl->chip_id == STM32F4_CHIP_ID)
+ if((sl->chip_id == STM32_CHIPID_F2) ||(sl->chip_id == STM32_CHIPID_F4))
stlink_write_debug32(sl, FLASH_F4_CR,
stlink_read_debug32(sl, FLASH_F4_CR) | (1 << FLASH_CR_MER));
else
}
static void __attribute__((unused)) clear_flash_cr_mer(stlink_t *sl) {
- if(sl->chip_id == STM32F4_CHIP_ID)
+ if((sl->chip_id == STM32_CHIPID_F2) ||(sl->chip_id == STM32_CHIPID_F4))
stlink_write_debug32(sl, FLASH_F4_CR,
stlink_read_debug32(sl, FLASH_F4_CR) & ~(1 << FLASH_CR_MER));
else
}
static void set_flash_cr_strt(stlink_t *sl) {
- if(sl->chip_id == STM32F4_CHIP_ID)
+ if((sl->chip_id == STM32_CHIPID_F2) ||(sl->chip_id == STM32_CHIPID_F4))
{
uint32_t x = read_flash_cr(sl);
x |= (1 << FLASH_F4_CR_STRT);
static inline uint32_t read_flash_sr(stlink_t *sl) {
uint32_t res;
- if(sl->chip_id==STM32F4_CHIP_ID)
+ if((sl->chip_id == STM32_CHIPID_F2) ||(sl->chip_id == STM32_CHIPID_F4))
res = stlink_read_debug32(sl, FLASH_F4_SR);
else
res = stlink_read_debug32(sl, FLASH_SR);
}
static inline unsigned int is_flash_busy(stlink_t *sl) {
- if(sl->chip_id==STM32F4_CHIP_ID)
+ if((sl->chip_id == STM32_CHIPID_F2) ||(sl->chip_id == STM32_CHIPID_F4))
return read_flash_sr(sl) & (1 << FLASH_F4_SR_BSY);
else
return read_flash_sr(sl) & (1 << FLASH_SR_BSY);
int stlink_load_device_params(stlink_t *sl) {
ILOG("Loading device parameters....\n");
const chip_params_t *params = NULL;
-
sl->core_id = stlink_core_id(sl);
uint32_t chip_id = stlink_chip_id(sl);
- /* Fix chip_id for F4 rev A errata */
- if (((chip_id & 0xFFF) == 0x411) && (sl->core_id == CORE_M4_R0)) {
- chip_id = 0x413;
+ sl->chip_id = chip_id & 0xfff;
+ /* Fix chip_id for F4 rev A errata , Read CPU ID, as CoreID is the same for F2/F4*/
+ if (sl->chip_id == 0x411) {
+ uint32_t cpuid = stlink_read_debug32(sl, 0xE000ED00);
+ if((cpuid & 0xfff0) == 0xc240)
+ sl->chip_id = 0x413;
}
- sl->chip_id = chip_id & 0xfff;
- for(size_t i = 0; i < sizeof(devices) / sizeof(devices[0]); i++) {
- if(devices[i].chip_id == sl->chip_id) {
- params = &devices[i];
- break;
- }
- }
+ for(size_t i = 0; i < sizeof(devices) / sizeof(devices[0]); i++) {
+ if(devices[i].chip_id == sl->chip_id) {
+ params = &devices[i];
+ break;
+ }
+ }
if (params == NULL) {
WLOG("unknown chip id! %#x\n", chip_id);
return -1;
// read flash size from hardware, if possible...
if (sl->chip_id == STM32_CHIPID_F2) {
- sl->flash_size = 0; // FIXME - need to work this out some other way, just set to max possible?
+ sl->flash_size = 0x100000; /* Use maximum, User must care!*/
} else if (sl->chip_id == STM32_CHIPID_F4) {
sl->flash_size = 0x100000; //todo: RM0090 error; size register same address as unique ID
} else {
mf->len = 0;
}
+/* Limit the block size to compare to 0x1800
+ Anything larger will stall the STLINK2
+ Maybe STLINK V1 needs smaller value!*/
static int check_file(stlink_t* sl, mapped_file_t* mf, stm32_addr_t addr) {
size_t off;
+ size_t n_cmp = sl->flash_pgsz;
+ if ( n_cmp > 0x1800)
+ n_cmp = 0x1800;
- for (off = 0; off < mf->len; off += sl->flash_pgsz) {
+ for (off = 0; off < mf->len; off += n_cmp) {
size_t aligned_size;
/* adjust last page size */
- size_t cmp_size = sl->flash_pgsz;
- if ((off + sl->flash_pgsz) > mf->len)
+ size_t cmp_size = n_cmp;
+ if ((off + n_cmp) > mf->len)
cmp_size = mf->len - off;
aligned_size = cmp_size;
}
uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr){
- if(sl->chip_id == STM32F4_CHIP_ID) {
+ if((sl->chip_id == STM32_CHIPID_F2) ||(sl->chip_id == STM32_CHIPID_F4)) {
uint32_t sector=calculate_F4_sectornum(flashaddr);
if (sector<4) sl->flash_pgsz=0x4000;
else if(sector<5) sl->flash_pgsz=0x10000;
*/
int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr)
{
- if (sl->chip_id == STM32F4_CHIP_ID)
+ if ((sl->chip_id == STM32_CHIPID_F2) ||(sl->chip_id == STM32_CHIPID_F4))
{
/* wait for ongoing op to finish */
wait_flash_busy(sl);
fprintf(stdout, "Erase Final CR:0x%x\n", read_flash_cr(sl));
#endif
}
- else if (sl->core_id == STM32L_CORE_ID)
+ else if (sl->chip_id == STM32_CHIPID_L1_MEDIUM)
{
uint32_t val;
const uint8_t* loader_code;
size_t loader_size;
- if (sl->core_id == STM32L_CORE_ID) /* stm32l */
+ if (sl->chip_id == STM32_CHIPID_L1_MEDIUM) /* stm32l */
{
loader_code = loader_code_stm32l;
loader_size = sizeof(loader_code_stm32l);
*/
int stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, unsigned length) {
size_t off;
- if (sl->chip_id == STM32_CHIPID_F4) {
- DLOG("(FIXME)Skipping verification for F4, not enough ram (yet)\n");
- return 0;
- }
+ size_t cmp_size = (sl->flash_pgsz > 0x1800)? 0x1800:sl->flash_pgsz;
ILOG("Starting verification of write complete\n");
- for (off = 0; off < length; off += sl->flash_pgsz) {
+ for (off = 0; off < length; off += cmp_size) {
size_t aligned_size;
/* adjust last page size */
- size_t cmp_size = sl->flash_pgsz;
- if ((off + sl->flash_pgsz) > length)
+ if ((off + cmp_size) > length)
cmp_size = length - off;
aligned_size = cmp_size;
ILOG("Finished erasing %d pages of %d (%#x) bytes\n",
page_count, sl->flash_pgsz, sl->flash_pgsz);
- if (sl->chip_id == STM32F4_CHIP_ID) {
+ if ((sl->chip_id == STM32_CHIPID_F2) ||(sl->chip_id == STM32_CHIPID_F4)) {
/* todo: check write operation */
/* First unlock the cr */
/* show progress. writing procedure is slow
and previous errors are misleading */
const uint32_t pgnum = (off / PROGRESS_CHUNK_SIZE)+1;
- const uint32_t pgcount = len / PROGRESS_CHUNK_SIZE;
+ const uint32_t pgcount = len / PROGRESS_CHUNK_SIZE +1;
fprintf(stdout, "Writing %ukB chunk %u out of %u\n", PROGRESS_CHUNK_SIZE/1024, pgnum, pgcount);
}
}
} //STM32F4END
- else if (sl->core_id == STM32L_CORE_ID) {
+ else if (sl->chip_id == STM32_CHIPID_L1_MEDIUM) {
/* use fast word write. todo: half page. */
uint32_t val;
fprintf(stdout, "\r");
if ((off % sl->flash_pgsz) > (sl->flash_pgsz -5)) {
- fprintf(stdout, "\r%3u/%u pages written",
+ fprintf(stdout, "\r%3zd/%3zd pages written",
off/sl->flash_pgsz, len/sl->flash_pgsz);
fflush(stdout);
}
return -1;
}
- if (sl->core_id == STM32L_CORE_ID) {
+ if (sl->chip_id == STM32_CHIPID_L1_MEDIUM) {
size_t count = size / sizeof(uint32_t);
if (size % sizeof(uint32_t)) ++count;
}
/* check written byte count */
- if (sl->core_id == STM32L_CORE_ID) {
+ if (sl->chip_id == STM32_CHIPID_L1_MEDIUM) {
size_t count = size / sizeof(uint32_t);
if (size % sizeof(uint32_t)) ++count;