sl->backend->read_all_regs(sl, regp);
}
+void stlink_read_all_unsupported_regs(stlink_t *sl, reg *regp) {
+ DLOG("*** stlink_read_all_unsupported_regs ***\n");
+ sl->backend->read_all_unsupported_regs(sl, regp);
+}
+
void stlink_write_reg(stlink_t *sl, uint32_t reg, int idx) {
DLOG("*** stlink_write_reg\n");
sl->backend->write_reg(sl, reg, idx);
sl->backend->read_reg(sl, r_idx, regp);
}
+void stlink_read_unsupported_reg(stlink_t *sl, int r_idx, reg *regp) {
+ int r_convert;
+
+ DLOG("*** stlink_read_unsupported_reg\n");
+ DLOG(" (%d) ***\n", r_idx);
+
+ /* Convert to values used by DCRSR */
+ if (r_idx >= 0x1C && r_idx <= 0x1F) { /* primask, basepri, faultmask, or control */
+ r_convert = 0x14;
+ } else if (r_idx == 0x40) { /* FPSCR */
+ r_convert = 0x21;
+ } else if (r_idx >= 0x20 && r_idx < 0x40) {
+ r_convert = 0x40 + (r_idx - 0x20);
+ } else {
+ fprintf(stderr, "Error: register address must be in [0x1C..0x40]\n");
+ return;
+ }
+
+ sl->backend->read_unsupported_reg(sl, r_convert, regp);
+}
+
unsigned int is_core_halted(stlink_t *sl) {
/* return non zero if core is halted */
stlink_status(sl);
0x00, 0xbe
};
+ static const uint8_t loader_code_stm32f4[] = {
+ // flashloaders/stm32f4.s
+
+ 0x07, 0x4b,
+
+ 0x62, 0xb1,
+ 0x04, 0x68,
+ 0x0c, 0x60,
+
+ 0xdc, 0x89,
+ 0x14, 0xf0, 0x01, 0x0f,
+ 0xfb, 0xd1,
+ 0x00, 0xf1, 0x04, 0x00,
+ 0x01, 0xf1, 0x04, 0x01,
+ 0xa2, 0xf1, 0x01, 0x02,
+ 0xf1, 0xe7,
+
+ 0x00, 0xbe,
+
+ 0x00, 0x3c, 0x02, 0x40,
+ };
+
const uint8_t* loader_code;
size_t loader_size;
loader_code = loader_code_stm32vl;
loader_size = sizeof(loader_code_stm32vl);
}
+ else if (sl->chip_id == STM32_CHIPID_F2 || sl->chip_id == STM32_CHIPID_F4)
+ {
+ loader_code = loader_code_stm32f4;
+ loader_size = sizeof(loader_code_stm32f4);
+ }
else
{
WLOG("unknown coreid, not sure what flash loader to use, aborting!: %x\n", sl->core_id);
if (sl->verbose >= 1) {
/* show progress. writing procedure is slow
and previous errors are misleading */
- fprintf(stdout, "\r%3u/%u halfpages written", count, num_half_pages);
+ fprintf(stdout, "\r%3u/%u halfpages written", count + 1, num_half_pages);
fflush(stdout);
}
while ((stlink_read_debug32(sl, STM32L_FLASH_SR) & (1 << 0)) != 0) {
if ((sl->chip_id == STM32_CHIPID_F2) ||(sl->chip_id == STM32_CHIPID_F4)) {
/* todo: check write operation */
+ ILOG("Starting Flash write for F2/F4\n");
+ /* flash loader initialization */
+ if (init_flash_loader(sl, &fl) == -1) {
+ WLOG("init_flash_loader() == -1\n");
+ return -1;
+ }
+
/* First unlock the cr */
unlock_flash_if(sl);
/* set programming mode */
set_flash_cr_pg(sl);
+ for(off = 0; off < len;) {
+ size_t size = len - off > 0x8000 ? 0x8000 : len - off;
+
+ printf("size: %u\n", size);
+
+ if (run_flash_loader(sl, &fl, addr + off, base + off, size) == -1) {
+ WLOG("run_flash_loader(%#zx) failed! == -1\n", addr + off);
+ return -1;
+ }
+
+ off += size;
+ }
+
+#if 0
#define PROGRESS_CHUNK_SIZE 0x1000
/* write a word in program memory */
for (off = 0; off < len; off += sizeof(uint32_t)) {
wait_flash_busy(sl);
}
+#endif
/* Relock flash */
lock_flash(sl);
stlink_write_reg(sl, 0, 3); /* flash bank 0 (input) */
stlink_write_reg(sl, fl->loader_addr, 15); /* pc register */
+ } else if (sl->chip_id == STM32_CHIPID_F2 || sl->chip_id == STM32_CHIPID_F4) {
+
+ size_t count = size / sizeof(uint32_t);
+ if (size % sizeof(uint32_t)) ++count;
+
+ /* setup core */
+ stlink_write_reg(sl, fl->buf_addr, 0); /* source */
+ stlink_write_reg(sl, target, 1); /* target */
+ stlink_write_reg(sl, count, 2); /* count (32 bits words) */
+ stlink_write_reg(sl, fl->loader_addr, 15); /* pc register */
+
} else {
fprintf(stderr, "unknown coreid: 0x%x\n", sl->core_id);
return -1;
return -1;
}
+ } else if (sl->chip_id == STM32_CHIPID_F2 || sl->chip_id == STM32_CHIPID_F4) {
+
+ stlink_read_reg(sl, 2, &rr);
+ if (rr.r[2] != 0) {
+ fprintf(stderr, "write error, count == %u\n", rr.r[2]);
+ return -1;
+ }
+
} else {
fprintf(stderr, "unknown coreid: 0x%x\n", sl->core_id);