#define FLASH_L1_FPRG 10
#define FLASH_L1_PROG 3
+//32L4 register base is at FLASH_REGS_ADDR (0x40022000)
+#define STM32L4_FLASH_KEYR (FLASH_REGS_ADDR + 0x08)
+#define STM32L4_FLASH_SR (FLASH_REGS_ADDR + 0x10)
+#define STM32L4_FLASH_CR (FLASH_REGS_ADDR + 0x14)
+#define STM32L4_FLASH_OPTR (FLASH_REGS_ADDR + 0x20)
+
+#define STM32L4_FLASH_SR_BSY 16
+#define STM32L4_FLASH_SR_ERRMASK 0x3f8 /* SR [9:3] */
+
+#define STM32L4_FLASH_CR_LOCK 31 /* Lock control register */
+#define STM32L4_FLASH_CR_PG 0 /* Program */
+#define STM32L4_FLASH_CR_PER 1 /* Page erase */
+#define STM32L4_FLASH_CR_MER1 2 /* Bank 1 erase */
+#define STM32L4_FLASH_CR_MER2 15 /* Bank 2 erase */
+#define STM32L4_FLASH_CR_STRT 16 /* Start command */
+#define STM32L4_FLASH_CR_BKER 11 /* Bank select for page erase */
+#define STM32L4_FLASH_CR_PNB 3 /* Page number (8 bits) */
+// Bits requesting flash operations (useful when we want to clear them)
+#define STM32L4_FLASH_CR_OPBITS \
+ ((1lu<<STM32L4_FLASH_CR_PG) | (1lu<<STM32L4_FLASH_CR_PER) \
+ | (1lu<<STM32L4_FLASH_CR_MER1) | (1lu<<STM32L4_FLASH_CR_MER1))
+// Page is fully specified by BKER and PNB
+#define STM32L4_FLASH_CR_PAGEMASK (0x1fflu << STM32L4_FLASH_CR_PNB)
+
+#define STM32L4_FLASH_OPTR_DUALBANK 21
+
//STM32L0x flash register base and offsets
//same as 32L1 above
+// RM0090 - DM00031020.pdf
#define STM32L0_FLASH_REGS_ADDR ((uint32_t)0x40022000)
#define FLASH_ACR_OFF ((uint32_t) 0x00)
#define FLASH_PECR_OFF ((uint32_t) 0x04)
static inline uint32_t read_flash_cr(stlink_t *sl) {
uint32_t res;
if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) ||(sl->chip_id == STM32_CHIPID_F4_DE) ||
- (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE))
+ (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) ||
+ (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7))
res = stlink_read_debug32(sl, FLASH_F4_CR);
+ else if (sl->chip_id == STM32_CHIPID_L4)
+ res = stlink_read_debug32(sl, STM32L4_FLASH_CR);
else
res = stlink_read_debug32(sl, FLASH_CR);
#if DEBUG_FLASH
static inline unsigned int is_flash_locked(stlink_t *sl) {
/* return non zero for true */
+ uint32_t cr = read_flash_cr(sl);
+
if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) ||
- (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) )
- return read_flash_cr(sl) & (1 << FLASH_F4_CR_LOCK);
+ (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) ||
+ (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7))
+ return cr & (1 << FLASH_F4_CR_LOCK);
+ else if (sl->chip_id == STM32_CHIPID_L4)
+ return cr & (1lu << STM32L4_FLASH_CR_LOCK);
else
- return read_flash_cr(sl) & (1 << FLASH_CR_LOCK);
+ return cr & (1 << FLASH_CR_LOCK);
}
static void unlock_flash(stlink_t *sl) {
the FPEC block until next reset.
*/
if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) ||
- (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE)) {
+ (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) ||
+ (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7)) {
stlink_write_debug32(sl, FLASH_F4_KEYR, FLASH_KEY1);
stlink_write_debug32(sl, FLASH_F4_KEYR, FLASH_KEY2);
+ } else if (sl->chip_id == STM32_CHIPID_L4) {
+ stlink_write_debug32(sl, STM32L4_FLASH_KEYR, FLASH_KEY1);
+ stlink_write_debug32(sl, STM32L4_FLASH_KEYR, FLASH_KEY2);
} else {
stlink_write_debug32(sl, FLASH_KEYR, FLASH_KEY1);
stlink_write_debug32(sl, FLASH_KEYR, FLASH_KEY2);
static void lock_flash(stlink_t *sl) {
if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) ||
- (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE)) {
+ (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) ||
+ (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7)) {
const uint32_t n = read_flash_cr(sl) | (1 << FLASH_F4_CR_LOCK);
stlink_write_debug32(sl, FLASH_F4_CR, n);
+ } else if (sl->chip_id == STM32_CHIPID_L4) {
+ const uint32_t n = read_flash_cr(sl) | (1lu << STM32L4_FLASH_CR_LOCK);
+ stlink_write_debug32(sl, STM32L4_FLASH_CR, n);
} else {
/* write to 1 only. reset by hw at unlock sequence */
const uint32_t n = read_flash_cr(sl) | (1 << FLASH_CR_LOCK);
static void set_flash_cr_pg(stlink_t *sl) {
if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) ||
- (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE)) {
+ (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) ||
+ (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7)) {
uint32_t x = read_flash_cr(sl);
x |= (1 << FLASH_CR_PG);
stlink_write_debug32(sl, FLASH_F4_CR, x);
+ } else if (sl->chip_id == STM32_CHIPID_L4) {
+ uint32_t x = read_flash_cr(sl);
+ x &=~ STM32L4_FLASH_CR_OPBITS;
+ x |= (1 << STM32L4_FLASH_CR_PG);
+ stlink_write_debug32(sl, STM32L4_FLASH_CR, x);
} else {
const uint32_t n = 1 << FLASH_CR_PG;
stlink_write_debug32(sl, FLASH_CR, n);
static void __attribute__((unused)) clear_flash_cr_pg(stlink_t *sl) {
const uint32_t n = read_flash_cr(sl) & ~(1 << FLASH_CR_PG);
if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) ||
- (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE))
+ (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) ||
+ (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7))
stlink_write_debug32(sl, FLASH_F4_CR, n);
else
stlink_write_debug32(sl, FLASH_CR, n);
static void set_flash_cr_mer(stlink_t *sl) {
if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) ||
- (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE))
+ (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) ||
+ (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7))
stlink_write_debug32(sl, FLASH_F4_CR,
stlink_read_debug32(sl, FLASH_F4_CR) | (1 << FLASH_CR_MER));
- else
+ else if (sl->chip_id == STM32_CHIPID_L4) {
+ uint32_t x = stlink_read_debug32(sl, STM32L4_FLASH_CR);
+ x &=~ STM32L4_FLASH_CR_OPBITS;
+ x |= (1lu << STM32L4_FLASH_CR_MER1) | (1lu << STM32L4_FLASH_CR_MER2);
+ stlink_write_debug32(sl, STM32L4_FLASH_CR, x);
+ } else
stlink_write_debug32(sl, FLASH_CR,
stlink_read_debug32(sl, FLASH_CR) | (1 << FLASH_CR_MER));
}
static void __attribute__((unused)) clear_flash_cr_mer(stlink_t *sl) {
if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) ||
- (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE))
+ (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) ||
+ (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7))
stlink_write_debug32(sl, FLASH_F4_CR,
stlink_read_debug32(sl, FLASH_F4_CR) & ~(1 << FLASH_CR_MER));
else
static void set_flash_cr_strt(stlink_t *sl) {
if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) ||
- (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE)) {
+ (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) ||
+ (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7)) {
uint32_t x = read_flash_cr(sl);
x |= (1 << FLASH_F4_CR_STRT);
stlink_write_debug32(sl, FLASH_F4_CR, x);
+ } else if (sl->chip_id == STM32_CHIPID_L4) {
+ uint32_t x = read_flash_cr(sl);
+ x |= (1lu << STM32L4_FLASH_CR_STRT);
+ stlink_write_debug32(sl, STM32L4_FLASH_CR, x);
} else {
stlink_write_debug32(sl, FLASH_CR,
stlink_read_debug32(sl, FLASH_CR) | (1 << FLASH_CR_STRT) );
static inline uint32_t read_flash_sr(stlink_t *sl) {
uint32_t res;
if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) ||
- (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE))
+ (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) ||
+ (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7))
res = stlink_read_debug32(sl, FLASH_F4_SR);
+ else if (sl->chip_id == STM32_CHIPID_L4)
+ res = stlink_read_debug32(sl, STM32L4_FLASH_SR);
else
res = stlink_read_debug32(sl, FLASH_SR);
//fprintf(stdout, "SR:0x%x\n", *(uint32_t*) sl->q_buf);
static inline unsigned int is_flash_busy(stlink_t *sl) {
if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) ||
- (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE))
+ (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) ||
+ (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7))
return read_flash_sr(sl) & (1 << FLASH_F4_SR_BSY);
+ else if (sl->chip_id == STM32_CHIPID_L4)
+ return read_flash_sr(sl) & (1 << STM32L4_FLASH_SR_BSY);
else
return read_flash_sr(sl) & (1 << FLASH_SR_BSY);
}
stlink_write_debug32(sl, FLASH_F4_CR, x);
}
+static inline void write_flash_cr_bker_pnb(stlink_t *sl, uint32_t n) {
+ uint32_t x = read_flash_cr(sl);
+ x &=~ STM32L4_FLASH_CR_OPBITS;
+ x &=~ STM32L4_FLASH_CR_PAGEMASK;
+ x |= (n << STM32L4_FLASH_CR_PNB);
+ x |= (1lu << STM32L4_FLASH_CR_PER);
+#if DEBUG_FLASH
+ fprintf(stdout, "BKER:PNB:0x%x 0x%x\n", x, n);
+#endif
+ stlink_write_debug32(sl, STM32L4_FLASH_CR, x);
+}
+
// Delegates to the backends...
void stlink_close(stlink_t *sl) {
if ((sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS) && ( flash_size == 0 )) {
sl->flash_size = 128 * 1024;
+ } else if (sl->chip_id == STM32_CHIPID_L1_CAT2) {
+ sl->flash_size = (flash_size & 0xff) * 1024;
} else if ((sl->chip_id & 0xFFF) == STM32_CHIPID_L1_HIGH) {
// 0 is 384k and 1 is 256k
if ( flash_size == 0 ) {
sl->sys_base = params->bootrom_base;
sl->sys_size = params->bootrom_size;
+ //medium and low devices have the same chipid. ram size depends on flash size.
+ //STM32F100xx datasheet Doc ID 16455 Table 2
+ if(sl->chip_id == STM32_CHIPID_F1_VL_MEDIUM_LOW && sl->flash_size < 64 * 1024){
+ sl->sram_size = 0x1000;
+ }
+
ILOG("Device connected is: %s, id %#x\n", params->description, chip_id);
// TODO make note of variable page size here.....
ILOG("SRAM size: %#x bytes (%d KiB), Flash: %#x bytes (%d KiB) in pages of %zd bytes\n",
int error = -1;
size_t off;
+ size_t len;
mapped_file_t mf = MAPPED_FILE_INITIALIZER;
} else if ((addr + mf.len) > (sl->sram_base + sl->sram_size)) {
fprintf(stderr, "addr too high\n");
goto on_error;
- } else if ((addr & 3) || (mf.len & 3)) {
+ } else if (addr & 3) {
/* todo */
- fprintf(stderr, "unaligned addr or size\n");
+ fprintf(stderr, "unaligned addr\n");
goto on_error;
}
+
+ len = mf.len;
+
+ if(len & 3) {
+ len -= len & 3;
+ }
+
/* do the copy by 1k blocks */
- for (off = 0; off < mf.len; off += 1024) {
+ for (off = 0; off < len; off += 1024) {
size_t size = 1024;
- if ((off + size) > mf.len)
- size = mf.len - off;
+ if ((off + size) > len)
+ size = len - off;
memcpy(sl->q_buf, mf.base + off, size);
stlink_write_mem32(sl, addr + off, size);
}
+ if(mf.len > len) {
+ memcpy(sl->q_buf, mf.base + len, mf.len - len);
+ stlink_write_mem8(sl, addr + len, mf.len - len);
+ }
+
/* check the file ha been written */
if (check_file(sl, &mf, addr) == -1) {
fprintf(stderr, "check_file() == -1\n");
int error = -1;
size_t off;
int num_empty = 0;
- unsigned char erased_pattern = (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS
- || sl->chip_id == STM32_CHIPID_L1_HIGH || sl->chip_id == STM32_CHIPID_L152_RE) ? 0:0xff;
+ unsigned char erased_pattern = (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_CAT2
+ || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS || sl->chip_id == STM32_CHIPID_L1_HIGH
+ || sl->chip_id == STM32_CHIPID_L152_RE) ? 0:0xff;
const int fd = open(path, O_RDWR | O_TRUNC | O_CREAT, 00700);
if (fd == -1) {
}
+// Returns BKER:PNB for the given page address
+uint32_t calculate_L4_page(stlink_t *sl, uint32_t flashaddr) {
+ uint32_t bker = 0;
+ uint32_t flashopt = stlink_read_debug32(sl, STM32L4_FLASH_OPTR);
+ flashaddr -= STM32_FLASH_BASE;
+ if (flashopt & (1lu << STM32L4_FLASH_OPTR_DUALBANK)) {
+ uint32_t banksize = sl->flash_size / 2;
+ if (flashaddr > banksize) {
+ flashaddr -= banksize;
+ bker = 0x100;
+ }
+ }
+ // For 1MB chips without the dual-bank option set, the page address will
+ // overflow into the BKER bit, which gives us the correct bank:page value.
+ return bker | flashaddr/sl->flash_pgsz;
+}
+
uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr){
if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) ||
- (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE)) {
+ (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) ||
+ (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7)) {
uint32_t sector=calculate_F4_sectornum(flashaddr);
if (sector>= 12) {
sector -= 12;
int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr)
{
if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) ||
- (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE)) {
+ (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) ||
+ (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7) || (sl->chip_id == STM32_CHIPID_L4)) {
/* wait for ongoing op to finish */
wait_flash_busy(sl);
unlock_flash_if(sl);
/* select the page to erase */
- // calculate the actual page from the address
- uint32_t sector=calculate_F4_sectornum(flashaddr);
+ if (sl->chip_id == STM32_CHIPID_L4) {
+ // calculate the actual bank+page from the address
+ uint32_t page = calculate_L4_page(sl, flashaddr);
+
+ write_flash_cr_bker_pnb(sl, page);
+ } else {
+ // calculate the actual page from the address
+ uint32_t sector=calculate_F4_sectornum(flashaddr);
- fprintf(stderr, "EraseFlash - Sector:0x%x Size:0x%x\n", sector, stlink_calculate_pagesize(sl, flashaddr));
+ fprintf(stderr, "EraseFlash - Sector:0x%x Size:0x%x\n", sector, stlink_calculate_pagesize(sl, flashaddr));
- //the SNB values for flash sectors in the second bank do not directly follow the values for the first bank on 2mb devices...
- if (sector >= 12) sector += 4;
+ //the SNB values for flash sectors in the second bank do not directly follow the values for the first bank on 2mb devices...
+ if (sector >= 12) sector += 4;
- write_flash_cr_snb(sl, sector);
+ write_flash_cr_snb(sl, sector);
+ }
/* start erase operation */
set_flash_cr_strt(sl);
#if DEBUG_FLASH
fprintf(stdout, "Erase Final CR:0x%x\n", read_flash_cr(sl));
#endif
- } else if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS
- || sl->chip_id == STM32_CHIPID_L1_HIGH || sl->chip_id == STM32_CHIPID_L152_RE
- || sl->chip_id == STM32_CHIPID_L0) {
+ } else if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_CAT2
+ || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS || sl->chip_id == STM32_CHIPID_L1_HIGH
+ || sl->chip_id == STM32_CHIPID_L152_RE || sl->chip_id == STM32_CHIPID_L0) {
uint32_t val;
uint32_t flash_regs_base;
} else if (sl->core_id == STM32VL_CORE_ID
|| sl->core_id == STM32F0_CORE_ID
|| sl->chip_id == STM32_CHIPID_F3
+ || sl->chip_id == STM32_CHIPID_F3_SMALL
+ || sl->chip_id == STM32_CHIPID_F303_HIGH
|| sl->chip_id == STM32_CHIPID_F37x
|| sl->chip_id == STM32_CHIPID_F334) {
/* wait for ongoing op to finish */
}
int stlink_erase_flash_mass(stlink_t *sl) {
- if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS
- || sl->chip_id == STM32_CHIPID_L1_HIGH || sl->chip_id == STM32_CHIPID_L152_RE
- || sl->chip_id == STM32_CHIPID_L0) {
+ if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_CAT2
+ || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS || sl->chip_id == STM32_CHIPID_L1_HIGH
+ || sl->chip_id == STM32_CHIPID_L152_RE || sl->chip_id == STM32_CHIPID_L0) {
/* erase each page */
int i = 0, num_pages = sl->flash_size/sl->flash_pgsz;
for (i = 0; i < num_pages; i++) {
0x04, 0xe0,
0x0c, 0x68,
- 0x04, 0x66,
+ 0x04, 0x60,
0x01, 0x33,
0x04, 0x31,
0x04, 0x30,
0x00, 0x3c, 0x02, 0x40,
};
+ static const uint8_t loader_code_stm32f4_lv[] = {
+ // flashloaders/stm32f4lv.s
+ 0x92, 0x00,
+
+ 0x08, 0x4b,
+ 0x62, 0xb1,
+ 0x04, 0x78,
+ 0x0c, 0x70,
+
+ 0xdc, 0x89,
+ 0x14, 0xf0, 0x01, 0x0f,
+ 0xfb, 0xd1,
+ 0x00, 0xf1, 0x01, 0x00,
+ 0x01, 0xf1, 0x01, 0x01,
+ 0xa2, 0xf1, 0x01, 0x02,
+ 0xf1, 0xe7,
+
+ 0x00, 0xbe,
+ 0x00, 0xbf,
+
+ 0x00, 0x3c, 0x02, 0x40,
+ };
+
+ static const uint8_t loader_code_stm32l4[] = {
+ // flashloaders/stm32l4.s
+ 0x08, 0x4b, // start: ldr r3, [pc, #32] ; <flash_base>
+ 0x72, 0xb1, // next: cbz r2, <done>
+ 0x04, 0x68, // ldr r4, [r0, #0]
+ 0x45, 0x68, // ldr r5, [r0, #4]
+ 0x0c, 0x60, // str r4, [r1, #0]
+ 0x4d, 0x60, // str r5, [r1, #4]
+ 0x5c, 0x8a, // wait: ldrh r4, [r3, #18]
+ 0x14, 0xf0, 0x01, 0x0f, // tst.w r4, #1
+ 0xfb, 0xd1, // bne.n <wait>
+ 0x00, 0xf1, 0x08, 0x00, // add.w r0, r0, #8
+ 0x01, 0xf1, 0x08, 0x01, // add.w r1, r1, #8
+ 0xa2, 0xf1, 0x02, 0x02, // add.w r2, r2, #2
+ 0xef, 0xe7, // b.n <next>
+ 0x00, 0xbe, // done: bkpt 0x0000
+ 0x00, 0x20, 0x02, 0x40 // flash_base: .word 0x40022000
+ };
+
+ static const uint8_t loader_code_stm32f7[] = {
+ 0x08, 0x4b,
+ 0x72, 0xb1,
+ 0x04, 0x68,
+ 0x0c, 0x60,
+ 0xbf, 0xf3, 0x4f, 0x8f, // DSB Memory barrier for in order flash write
+ 0xdc, 0x89,
+ 0x14, 0xf0, 0x01, 0x0f,
+ 0xfb, 0xd1,
+ 0x00, 0xf1, 0x04, 0x00,
+ 0x01, 0xf1, 0x04, 0x01,
+ 0xa2, 0xf1, 0x01, 0x02,
+ 0xef, 0xe7,
+ 0x00, 0xbe, // bkpt #0x00
+ 0x00, 0x3c, 0x02, 0x40,
+ };
+
const uint8_t* loader_code;
size_t loader_size;
- if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS
- || sl->chip_id == STM32_CHIPID_L1_HIGH || sl->chip_id == STM32_CHIPID_L152_RE) { /* stm32l */
+ if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_CAT2
+ || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS || sl->chip_id == STM32_CHIPID_L1_HIGH
+ || sl->chip_id == STM32_CHIPID_L152_RE) { /* stm32l */
loader_code = loader_code_stm32l;
loader_size = sizeof(loader_code_stm32l);
- } else if (sl->core_id == STM32VL_CORE_ID || sl->chip_id == STM32_CHIPID_F3 ||
- sl->chip_id == STM32_CHIPID_F37x || sl->chip_id == STM32_CHIPID_F334) {
+ } else if (sl->core_id == STM32VL_CORE_ID
+ || sl->chip_id == STM32_CHIPID_F3
+ || sl->chip_id == STM32_CHIPID_F3_SMALL
+ || sl->chip_id == STM32_CHIPID_F303_HIGH
+ || sl->chip_id == STM32_CHIPID_F37x
+ || sl->chip_id == STM32_CHIPID_F334) {
loader_code = loader_code_stm32vl;
loader_size = sizeof(loader_code_stm32vl);
} else if (sl->chip_id == STM32_CHIPID_F2 || sl->chip_id == STM32_CHIPID_F4 || (sl->chip_id == STM32_CHIPID_F4_DE) ||
- sl->chip_id == STM32_CHIPID_F4_LP || sl->chip_id == STM32_CHIPID_F4_HD || (sl->chip_id == STM32_CHIPID_F411RE)){
- loader_code = loader_code_stm32f4;
- loader_size = sizeof(loader_code_stm32f4);
- } else if (sl->chip_id == STM32_CHIPID_F0 || sl->chip_id == STM32_CHIPID_F0_CAN || sl->chip_id == STM32_CHIPID_F0_SMALL) {
+ sl->chip_id == STM32_CHIPID_F4_LP || sl->chip_id == STM32_CHIPID_F4_HD || (sl->chip_id == STM32_CHIPID_F411RE) ||
+ (sl->chip_id == STM32_CHIPID_F446)){
+ int voltage = stlink_target_voltage(sl);
+ if (voltage > 2700) {
+ loader_code = loader_code_stm32f4;
+ loader_size = sizeof(loader_code_stm32f4);
+ } else {
+ loader_code = loader_code_stm32f4_lv;
+ loader_size = sizeof(loader_code_stm32f4_lv);
+ }
+ } else if (sl->chip_id == STM32_CHIPID_F7){
+ loader_code = loader_code_stm32f7;
+ loader_size = sizeof(loader_code_stm32f7);
+ } else if (sl->chip_id == STM32_CHIPID_F0 || sl->chip_id == STM32_CHIPID_F04 || sl->chip_id == STM32_CHIPID_F0_CAN || sl->chip_id == STM32_CHIPID_F0_SMALL || sl->chip_id == STM32_CHIPID_F09X) {
loader_code = loader_code_stm32f0;
loader_size = sizeof(loader_code_stm32f0);
} else if (sl->chip_id == STM32_CHIPID_L0) {
- loader_code = loader_code_stm32l0;
- loader_size = sizeof(loader_code_stm32l0);
- } else {
+ loader_code = loader_code_stm32l0;
+ loader_size = sizeof(loader_code_stm32l0);
+ } else if (sl->chip_id == STM32_CHIPID_L4) {
+ loader_code = loader_code_stm32l4;
+ loader_size = sizeof(loader_code_stm32l4);
+ } else {
ELOG("unknown coreid, not sure what flash loader to use, aborting!: %x\n", sl->core_id);
return -1;
}
(sl->chip_id == STM32_CHIPID_F4_DE) ||
(sl->chip_id == STM32_CHIPID_F4_LP) ||
(sl->chip_id == STM32_CHIPID_F4_HD) ||
- (sl->chip_id == STM32_CHIPID_F411RE)) {
+ (sl->chip_id == STM32_CHIPID_F411RE) ||
+ (sl->chip_id == STM32_CHIPID_F446) ||
+ (sl->chip_id == STM32_CHIPID_F7) ||
+ (sl->chip_id == STM32_CHIPID_L4)) {
/* todo: check write operation */
- ILOG("Starting Flash write for F2/F4\n");
+ ILOG("Starting Flash write for F2/F4/L4\n");
/* flash loader initialization */
if (init_flash_loader(sl, &fl) == -1) {
ELOG("init_flash_loader() == -1\n");
unlock_flash_if(sl);
/* TODO: Check that Voltage range is 2.7 - 3.6 V */
- /* set parallelisim to 32 bit*/
- write_flash_cr_psiz(sl, 2);
+ if (sl->chip_id != STM32_CHIPID_L4) {
+ /* set parallelisim to 32 bit*/
+ int voltage = stlink_target_voltage(sl);
+ if (voltage > 2700) {
+ printf("enabling 32-bit flash writes\n");
+ write_flash_cr_psiz(sl, 2);
+ } else {
+ printf("Target voltage (%d mV) too low for 32-bit flash, using 8-bit flash writes\n", voltage);
+ write_flash_cr_psiz(sl, 0);
+ }
+ } else {
+ /* L4 does not have a byte-write mode */
+ int voltage = stlink_target_voltage(sl);
+ if (voltage <= 2700) {
+ printf("Target voltage (%d mV) too low for flash writes!\n", voltage);
+ return -1;
+ }
+ }
/* set programming mode */
set_flash_cr_pg(sl);
} //STM32F4END
- else if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS
- || sl->chip_id == STM32_CHIPID_L1_HIGH || sl->chip_id == STM32_CHIPID_L152_RE
- || sl->chip_id == STM32_CHIPID_L0) {
+ else if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_CAT2
+ || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS || sl->chip_id == STM32_CHIPID_L1_HIGH
+ || sl->chip_id == STM32_CHIPID_L152_RE || sl->chip_id == STM32_CHIPID_L0) {
/* use fast word write. todo: half page. */
uint32_t val;
uint32_t flash_regs_base;
} else if (sl->core_id == STM32VL_CORE_ID ||
sl->core_id == STM32F0_CORE_ID ||
sl->chip_id == STM32_CHIPID_F3 ||
+ sl->chip_id == STM32_CHIPID_F3_SMALL ||
+ sl->chip_id == STM32_CHIPID_F303_HIGH ||
sl->chip_id == STM32_CHIPID_F334 ||
sl->chip_id == STM32_CHIPID_F37x) {
ILOG("Starting Flash write for VL/F0/F3 core id\n");
/* write the file in flash at addr */
int err;
unsigned int num_empty = 0, index;
- unsigned char erased_pattern =(sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS
- || sl->chip_id == STM32_CHIPID_L1_HIGH || sl->chip_id == STM32_CHIPID_L152_RE )?0:0xff;
+ unsigned char erased_pattern = (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_CAT2
+ || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS || sl->chip_id == STM32_CHIPID_L1_HIGH
+ || sl->chip_id == STM32_CHIPID_L152_RE) ? 0:0xff;
mapped_file_t mf = MAPPED_FILE_INITIALIZER;
if (map_file(&mf, path) == -1) {
ELOG("map_file() == -1\n");
return -1;
}
- if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS
- || sl->chip_id == STM32_CHIPID_L1_HIGH || sl->chip_id == STM32_CHIPID_L152_RE
- || sl->chip_id == STM32_CHIPID_L0) {
+ if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_CAT2
+ || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS || sl->chip_id == STM32_CHIPID_L1_HIGH
+ || sl->chip_id == STM32_CHIPID_L152_RE || sl->chip_id == STM32_CHIPID_L0) {
size_t count = size / sizeof(uint32_t);
if (size % sizeof(uint32_t)) ++count;
} else if (sl->core_id == STM32VL_CORE_ID ||
sl->core_id == STM32F0_CORE_ID ||
sl->chip_id == STM32_CHIPID_F3 ||
+ sl->chip_id == STM32_CHIPID_F3_SMALL ||
+ sl->chip_id == STM32_CHIPID_F303_HIGH ||
sl->chip_id == STM32_CHIPID_F37x ||
sl->chip_id == STM32_CHIPID_F334) {
stlink_write_reg(sl, fl->loader_addr, 15); /* pc register */
} else if (sl->chip_id == STM32_CHIPID_F2 || sl->chip_id == STM32_CHIPID_F4 || (sl->chip_id == STM32_CHIPID_F4_DE) ||
- sl->chip_id == STM32_CHIPID_F4_LP || sl->chip_id == STM32_CHIPID_F4_HD || (sl->chip_id == STM32_CHIPID_F411RE)) {
+ sl->chip_id == STM32_CHIPID_F4_LP || sl->chip_id == STM32_CHIPID_F4_HD || (sl->chip_id == STM32_CHIPID_F411RE) ||
+ (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7) || (sl->chip_id == STM32_CHIPID_L4)) {
size_t count = size / sizeof(uint32_t);
if (size % sizeof(uint32_t)) ++count;
+ if (sl->chip_id == STM32_CHIPID_L4) {
+ if (count % 2) ++count;
+ }
/* setup core */
stlink_write_reg(sl, fl->buf_addr, 0); /* source */
}
/* check written byte count */
- if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS
- || sl->chip_id == STM32_CHIPID_L1_HIGH || sl->chip_id == STM32_CHIPID_L152_RE
- || sl->chip_id == STM32_CHIPID_L0) {
+ if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_CAT2
+ || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS || sl->chip_id == STM32_CHIPID_L1_HIGH
+ || sl->chip_id == STM32_CHIPID_L152_RE || sl->chip_id == STM32_CHIPID_L0) {
size_t count = size / sizeof(uint32_t);
if (size % sizeof(uint32_t)) ++count;
} else if (sl->core_id == STM32VL_CORE_ID ||
sl->core_id == STM32F0_CORE_ID ||
sl->chip_id == STM32_CHIPID_F3 ||
+ sl->chip_id == STM32_CHIPID_F3_SMALL ||
+ sl->chip_id == STM32_CHIPID_F303_HIGH ||
sl->chip_id == STM32_CHIPID_F37x ||
sl->chip_id == STM32_CHIPID_F334) {
}
} else if (sl->chip_id == STM32_CHIPID_F2 || sl->chip_id == STM32_CHIPID_F4 || (sl->chip_id == STM32_CHIPID_F4_DE) ||
- sl->chip_id == STM32_CHIPID_F4_LP || sl->chip_id == STM32_CHIPID_F4_HD || (sl->chip_id == STM32_CHIPID_F411RE)) {
+ sl->chip_id == STM32_CHIPID_F4_LP || sl->chip_id == STM32_CHIPID_F4_HD || (sl->chip_id == STM32_CHIPID_F411RE) ||
+ (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7) || (sl->chip_id == STM32_CHIPID_L4)) {
stlink_read_reg(sl, 2, &rr);
if (rr.r[2] != 0) {