#define STRCASECMP strcasecmp
#endif
+/****************************************************************/
+/****************************************************************/
+
+peepCommand peepCommands[] = {
+
+ {NOTBITSKIP, "_NOTBITSKIP_"},
+ {BITSKIP, "_BITSKIP_"},
+ {INVERTBITSKIP, "_INVERTBITSKIP_"},
+
+ {-1, NULL}
+};
+
+
// Eventually this will go into device dependent files:
pCodeOpReg pc_status = {{PO_STATUS, "STATUS"}, -1, NULL,0,NULL};
static hTab *pic14MnemonicsHash = NULL;
+static hTab *pic14pCodePeepCommandsHash = NULL;
static pFile *the_pFile = NULL;
-static int peepOptimizing = 1;
+static int peepOptimizing = 0;
static int GpCodeSequenceNumber = 1;
static int GpcFlowSeq = 1;
#define isPCI(x) ((PCODE(x)->type == PC_OPCODE))
#define isPCI_BRANCH(x) ((PCODE(x)->type == PC_OPCODE) && PCI(x)->isBranch)
#define isPCI_SKIP(x) ((PCODE(x)->type == PC_OPCODE) && PCI(x)->isSkip)
+#define isPCI_BITSKIP(x)((PCODE(x)->type == PC_OPCODE) && PCI(x)->isSkip && PCI(x)->isBitInst)
#define isPCFL(x) ((PCODE(x)->type == PC_FLOW))
#define isPCF(x) ((PCODE(x)->type == PC_FUNCTION))
#define isCALL(x) ((isPCI(x)) && (PCI(x)->op == POC_CALL))
2, // num ops
1,0, // dest, bit instruction
0,0, // branch, skip
+ POC_NOP,
(PCC_W | PCC_REGISTER), // inCond
(PCC_REGISTER | PCC_Z) // outCond
};
// genericAnalyze,
genericDestruct,
genericPrint},
- POC_ADDWF,
+ POC_ADDFW,
"ADDWF",
NULL, // from branch
NULL, // to branch
2, // num ops
0,0, // dest, bit instruction
0,0, // branch, skip
+ POC_NOP,
(PCC_W | PCC_REGISTER), // inCond
(PCC_W | PCC_Z) // outCond
};
1, // num ops
0,0, // dest, bit instruction
0,0, // branch, skip
+ POC_NOP,
PCC_W, // inCond
(PCC_W | PCC_Z | PCC_C | PCC_DC) // outCond
};
1, // num ops
0,0, // dest, bit instruction
0,0, // branch, skip
+ POC_NOP,
PCC_W, // inCond
(PCC_W | PCC_Z) // outCond
};
2, // num ops
1,0, // dest, bit instruction
0,0, // branch, skip
+ POC_NOP,
(PCC_W | PCC_REGISTER), // inCond
(PCC_REGISTER | PCC_Z) // outCond
};
// genericAnalyze,
genericDestruct,
genericPrint},
- POC_ANDWF,
+ POC_ANDFW,
"ANDWF",
NULL, // from branch
NULL, // to branch
2, // num ops
0,0, // dest, bit instruction
0,0, // branch, skip
+ POC_NOP,
(PCC_W | PCC_REGISTER), // inCond
(PCC_W | PCC_Z) // outCond
};
2, // num ops
1,1, // dest, bit instruction
0,0, // branch, skip
+ POC_BSF,
PCC_REGISTER, // inCond
PCC_REGISTER // outCond
};
2, // num ops
1,1, // dest, bit instruction
0,0, // branch, skip
+ POC_BCF,
PCC_REGISTER, // inCond
PCC_REGISTER // outCond
};
2, // num ops
0,1, // dest, bit instruction
1,1, // branch, skip
+ POC_BTFSS,
PCC_REGISTER, // inCond
PCC_NONE // outCond
};
2, // num ops
0,1, // dest, bit instruction
1,1, // branch, skip
+ POC_BTFSC,
PCC_REGISTER, // inCond
PCC_NONE // outCond
};
1, // num ops
0,0, // dest, bit instruction
1,0, // branch, skip
+ POC_NOP,
PCC_NONE, // inCond
PCC_NONE // outCond
};
2, // num ops
1,0, // dest, bit instruction
0,0, // branch, skip
+ POC_NOP,
PCC_REGISTER, // inCond
PCC_REGISTER // outCond
};
2, // num ops
0,0, // dest, bit instruction
0,0, // branch, skip
+ POC_NOP,
PCC_REGISTER, // inCond
PCC_W // outCond
};
1, // num ops
0,0, // dest, bit instruction
0,0, // branch, skip
+ POC_NOP,
PCC_REGISTER, // inCond
PCC_REGISTER // outCond
};
0, // num ops
0,0, // dest, bit instruction
0,0, // branch, skip
+ POC_NOP,
PCC_W, // inCond
PCC_W // outCond
};
2, // num ops
1,0, // dest, bit instruction
0,0, // branch, skip
+ POC_NOP,
PCC_REGISTER, // inCond
PCC_REGISTER // outCond
};
2, // num ops
0,0, // dest, bit instruction
0,0, // branch, skip
+ POC_NOP,
PCC_REGISTER, // inCond
PCC_W // outCond
};
2, // num ops
1,0, // dest, bit instruction
1,1, // branch, skip
+ POC_NOP,
PCC_REGISTER, // inCond
PCC_REGISTER // outCond
};
2, // num ops
0,0, // dest, bit instruction
1,1, // branch, skip
+ POC_NOP,
PCC_REGISTER, // inCond
PCC_W // outCond
};
1, // num ops
0,0, // dest, bit instruction
1,0, // branch, skip
+ POC_NOP,
PCC_NONE, // inCond
PCC_NONE // outCond
};
-
pCodeInstruction pciINCF = {
{PC_OPCODE, NULL, NULL, 0, NULL,
// genericAnalyze,
2, // num ops
1,0, // dest, bit instruction
0,0, // branch, skip
+ POC_NOP,
PCC_REGISTER, // inCond
PCC_REGISTER // outCond
};
2, // num ops
0,0, // dest, bit instruction
0,0, // branch, skip
+ POC_NOP,
PCC_REGISTER, // inCond
PCC_W // outCond
};
2, // num ops
1,0, // dest, bit instruction
1,1, // branch, skip
+ POC_NOP,
PCC_REGISTER, // inCond
PCC_REGISTER // outCond
};
2, // num ops
0,0, // dest, bit instruction
1,1, // branch, skip
+ POC_NOP,
PCC_REGISTER, // inCond
PCC_W // outCond
};
2, // num ops
1,0, // dest, bit instruction
0,0, // branch, skip
+ POC_NOP,
(PCC_W | PCC_REGISTER), // inCond
(PCC_REGISTER | PCC_Z) // outCond
};
// genericAnalyze,
genericDestruct,
genericPrint},
- POC_IORWF,
+ POC_IORFW,
"IORWF",
NULL, // from branch
NULL, // to branch
2, // num ops
0,0, // dest, bit instruction
0,0, // branch, skip
+ POC_NOP,
(PCC_W | PCC_REGISTER), // inCond
(PCC_W | PCC_Z) // outCond
};
1, // num ops
0,0, // dest, bit instruction
0,0, // branch, skip
+ POC_NOP,
PCC_W, // inCond
(PCC_W | PCC_Z) // outCond
};
2, // num ops
1,0, // dest, bit instruction
0,0, // branch, skip
+ POC_NOP,
PCC_REGISTER, // inCond
PCC_Z // outCond
};
2, // num ops
0,0, // dest, bit instruction
0,0, // branch, skip
+ POC_NOP,
PCC_REGISTER, // inCond
(PCC_W | PCC_Z) // outCond
};
1, // num ops
0,0, // dest, bit instruction
0,0, // branch, skip
+ POC_NOP,
PCC_W, // inCond
PCC_REGISTER // outCond
};
1, // num ops
0,0, // dest, bit instruction
0,0, // branch, skip
+ POC_NOP,
PCC_NONE, // inCond
PCC_W // outCond
};
0, // num ops
0,0, // dest, bit instruction
0,0, // branch, skip
+ POC_NOP,
PCC_NONE, // inCond
PCC_NONE // outCond
};
0, // num ops
0,0, // dest, bit instruction
1,0, // branch, skip
+ POC_NOP,
PCC_NONE, // inCond
PCC_NONE // outCond (not true... affects the GIE bit too)
};
1, // num ops
0,0, // dest, bit instruction
1,0, // branch, skip
+ POC_NOP,
PCC_NONE, // inCond
PCC_W // outCond
};
0, // num ops
0,0, // dest, bit instruction
1,0, // branch, skip
+ POC_NOP,
PCC_NONE, // inCond
PCC_NONE // outCond
};
2, // num ops
1,0, // dest, bit instruction
0,0, // branch, skip
+ POC_NOP,
(PCC_C | PCC_REGISTER), // inCond
(PCC_REGISTER | PCC_Z | PCC_C | PCC_DC) // outCond
};
2, // num ops
0,0, // dest, bit instruction
0,0, // branch, skip
+ POC_NOP,
(PCC_C | PCC_REGISTER), // inCond
(PCC_W | PCC_Z | PCC_C | PCC_DC) // outCond
};
2, // num ops
1,0, // dest, bit instruction
0,0, // branch, skip
+ POC_NOP,
(PCC_C | PCC_REGISTER), // inCond
(PCC_REGISTER | PCC_Z | PCC_C | PCC_DC) // outCond
};
2, // num ops
0,0, // dest, bit instruction
0,0, // branch, skip
+ POC_NOP,
(PCC_C | PCC_REGISTER), // inCond
(PCC_W | PCC_Z | PCC_C | PCC_DC) // outCond
};
2, // num ops
1,0, // dest, bit instruction
0,0, // branch, skip
+ POC_NOP,
(PCC_W | PCC_REGISTER), // inCond
(PCC_REGISTER | PCC_Z) // outCond
};
// genericAnalyze,
genericDestruct,
genericPrint},
- POC_SUBWF,
+ POC_SUBFW,
"SUBWF",
NULL, // from branch
NULL, // to branch
2, // num ops
0,0, // dest, bit instruction
0,0, // branch, skip
+ POC_NOP,
(PCC_W | PCC_REGISTER), // inCond
(PCC_W | PCC_Z) // outCond
};
1, // num ops
0,0, // dest, bit instruction
0,0, // branch, skip
+ POC_NOP,
PCC_W, // inCond
(PCC_W | PCC_Z | PCC_C | PCC_DC) // outCond
};
2, // num ops
1,0, // dest, bit instruction
0,0, // branch, skip
+ POC_NOP,
(PCC_REGISTER), // inCond
(PCC_REGISTER) // outCond
};
2, // num ops
0,0, // dest, bit instruction
0,0, // branch, skip
+ POC_NOP,
(PCC_REGISTER), // inCond
(PCC_W) // outCond
};
1, // num ops
0,0, // dest, bit instruction
0,0, // branch, skip
+ POC_NOP,
PCC_NONE, // inCond
PCC_REGISTER // outCond
};
2, // num ops
1,0, // dest, bit instruction
0,0, // branch, skip
+ POC_NOP,
(PCC_W | PCC_REGISTER), // inCond
(PCC_REGISTER | PCC_Z) // outCond
};
// genericAnalyze,
genericDestruct,
genericPrint},
- POC_XORWF,
+ POC_XORFW,
"XORWF",
NULL, // from branch
NULL, // to branch
2, // num ops
0,0, // dest, bit instruction
0,0, // branch, skip
+ POC_NOP,
(PCC_W | PCC_REGISTER), // inCond
(PCC_W | PCC_Z) // outCond
};
1, // num ops
0,0, // dest, bit instruction
0,0, // branch, skip
+ POC_NOP,
PCC_W, // inCond
(PCC_W | PCC_Z | PCC_C | PCC_DC) // outCond
};
extern void initStack(int base_address, int size);
extern regs *allocProcessorRegister(int rIdx, char * name, short po_type, int alias);
extern regs *allocInternalRegister(int rIdx, char * name, short po_type, int alias);
-extern void init_pic(void);
+extern void init_pic(char *);
void pCodeInitRegisters(void)
{
initStack(0x38, 8);
- init_pic();
+ init_pic(port->processor);
pc_status.r = allocProcessorRegister(IDX_STATUS,"STATUS", PO_STATUS, 0x80);
pc_pcl.r = allocProcessorRegister(IDX_PCL,"PCL", PO_PCL, 0x80);
if(mnemonics_initialized)
return;
+//FIXME - probably should NULL out the array before making the assignments
+//since we check the array contents below this initialization.
+
pic14Mnemonics[POC_ADDLW] = &pciADDLW;
pic14Mnemonics[POC_ADDWF] = &pciADDWF;
pic14Mnemonics[POC_ADDFW] = &pciADDFW;
mnemonics_initialized = 1;
}
+int getpCodePeepCommand(char *cmd);
+
int getpCode(char *mnem,unsigned dest)
{
return -1;
}
+/*-----------------------------------------------------------------*
+ * pic14initpCodePeepCommands
+ *
+ *-----------------------------------------------------------------*/
+void pic14initpCodePeepCommands(void)
+{
+
+ int key, i;
+ peepCommand *pcmd;
+
+ i = 0;
+ do {
+ hTabAddItem(&pic14pCodePeepCommandsHash,
+ mnem2key(peepCommands[i].cmd), &peepCommands[i]);
+ i++;
+ } while (peepCommands[i].cmd);
+
+ pcmd = hTabFirstItem(pic14pCodePeepCommandsHash, &key);
+
+ while(pcmd) {
+ //fprintf(stderr, "peep command %s key %d\n",pcmd->cmd,pcmd->id);
+ pcmd = hTabNextItem(pic14pCodePeepCommandsHash, &key);
+ }
+
+}
+
+/*-----------------------------------------------------------------
+ *
+ *
+ *-----------------------------------------------------------------*/
+
+int getpCodePeepCommand(char *cmd)
+{
+
+ peepCommand *pcmd;
+ int key = mnem2key(cmd);
+
+
+ pcmd = hTabFirstItemWK(pic14pCodePeepCommandsHash, key);
+
+ while(pcmd) {
+ // fprintf(stderr," comparing %s to %s\n",pcmd->cmd,cmd);
+ if(STRCASECMP(pcmd->cmd, cmd) == 0) {
+ return pcmd->id;
+ }
+
+ pcmd = hTabNextItemWK (pic14pCodePeepCommandsHash);
+
+ }
+
+ return -1;
+}
+
char getpBlock_dbName(pBlock *pb)
{
if(!pb)
pcw->operand = optional_operand;
pcw->label = optional_label;
+ pcw->mustBeBitSkipInst = 0;
+ pcw->mustNotBeBitSkipInst = 0;
+ pcw->invertBitSkipInst = 0;
+
return ( (pCode *)pcw);
}
{
pCodeOp *pcop;
-
pcop = Safe_calloc(1,sizeof(pCodeOpImmd) );
pcop->type = PO_IMMEDIATE;
if(name) {
pcop->name = Safe_strdup(name);
+ fprintf(stderr,"%s %s %d\n",__FUNCTION__,name,offset);
} else {
pcop->name = NULL;
}
/*-----------------------------------------------------------------*/
/*-----------------------------------------------------------------*/
-pCodeOp *newpCodeOpWild(int id, pCodePeep *pcp, pCodeOp *subtype)
+pCodeOp *newpCodeOpWild(int id, pCodeWildBlock *pcwb, pCodeOp *subtype)
{
char *s = buffer;
pCodeOp *pcop;
- if(!pcp || !subtype) {
+ if(!pcwb || !subtype) {
fprintf(stderr, "Wild opcode declaration error: %s-%d\n",__FILE__,__LINE__);
exit(1);
}
pcop->name = Safe_strdup(s);
PCOW(pcop)->id = id;
- PCOW(pcop)->pcp = pcp;
+ PCOW(pcop)->pcwb = pcwb;
PCOW(pcop)->subtype = subtype;
PCOW(pcop)->matched = NULL;
return pcop;
}
+/*-----------------------------------------------------------------*
+ * pCodeOp *newpCodeOpReg(int rIdx) - allocate a new register
+ *
+ * If rIdx >=0 then a specific register from the set of registers
+ * will be selected. If rIdx <0, then a new register will be searched
+ * for.
+ *-----------------------------------------------------------------*/
+
pCodeOp *newpCodeOpReg(int rIdx)
{
pCodeOp *pcop;
pcop = Safe_calloc(1,sizeof(pCodeOpReg) );
pcop->name = NULL;
- PCOR(pcop)->rIdx = rIdx;
- PCOR(pcop)->r = pic14_regWithIdx(rIdx);
+
+ if(rIdx >= 0) {
+ PCOR(pcop)->rIdx = rIdx;
+ PCOR(pcop)->r = pic14_regWithIdx(rIdx);
+ } else {
+ PCOR(pcop)->r = pic14_findFreeReg(REG_GPR);
+
+ if(PCOR(pcop)->r)
+ PCOR(pcop)->rIdx = PCOR(pcop)->r->rIdx;
+ //fprintf(stderr, "newpcodeOpReg - rIdx = %d\n", PCOR(pcop)->r->rIdx);
+ }
+
pcop->type = PCOR(pcop)->r->pc_type;
return pcop;
}
+
pCodeOp *newpCodeOpRegFromStr(char *name)
{
pCodeOp *pcop;
pcop = Safe_calloc(1,sizeof(pCodeOpReg) );
- PCOR(pcop)->r = allocRegByName(name);
+ PCOR(pcop)->r = allocRegByName(name, 1);
PCOR(pcop)->rIdx = PCOR(pcop)->r->rIdx;
pcop->type = PCOR(pcop)->r->pc_type;
pcop->name = PCOR(pcop)->r->name;
case PO_LABEL:
pcop = newpCodeOpLabel(NULL,-1);
break;
+ case PO_GPR_TEMP:
+ pcop = newpCodeOpReg(-1);
+ break;
default:
pcop = Safe_calloc(1,sizeof(pCodeOp) );
case PO_IMMEDIATE:
s = buffer;
size = sizeof(buffer);
+
+
+/*
if( PCOI(pcc->pcop)->offset && PCOI(pcc->pcop)->offset<4) {
SAFE_snprintf(&s,&size,"((%s >> %d)&0xff)",
pcc->pcop->name,
8 * PCOI(pcc->pcop)->offset );
} else
SAFE_snprintf(&s,&size,"LOW(%s)",pcc->pcop->name);
+*/
-
+ if( PCOI(pcc->pcop)->offset && PCOI(pcc->pcop)->offset<4) {
+ SAFE_snprintf(&s,&size,"(%s + %d)",
+ pcc->pcop->name,
+ PCOI(pcc->pcop)->offset );
+ } else
+ SAFE_snprintf(&s,&size,"%s",pcc->pcop->name);
+ return buffer;
+
+ case PO_DIR:
+ s = buffer;
+ size = sizeof(buffer);
+ if( PCOR(pcc->pcop)->instance) {
+ SAFE_snprintf(&s,&size,"(%s + %d)",
+ pcc->pcop->name,
+ PCOR(pcc->pcop)->instance );
+ fprintf(stderr,"PO_DIR %s\n",buffer);
+ } else
+ SAFE_snprintf(&s,&size,"%s",pcc->pcop->name);
return buffer;
default:
}
/*-----------------------------------------------------------------*/
-/* popCopy - copy a pcode operator */
+/* popCopyGPR2Bit - copy a pcode operator */
/*-----------------------------------------------------------------*/
+
pCodeOp *popCopyGPR2Bit(pCodeOp *pc, int bitval)
{
pCodeOp *pcop;
if (PCF(pc)->fname) {
if(STRCASECMP(PCF(pc)->fname, "_main") == 0) {
- fprintf(stderr," found main \n");
+ //fprintf(stderr," found main \n");
pb->cmemmap = NULL; /* FIXME do we need to free ? */
pb->dbName = 'M';
}
projects / fw / sdcc / blobdiff