extern void RegsUnMapLiveRanges(void);
extern void BuildFlowTree(pBlock *pb);
extern void pCodeRegOptimizeRegUsage(int level);
+extern int picIsInitialized(void);
/****************************************************************/
/* Forward declarations */
PCC_W // outCond
};
+pCodeInstruction pciCLRWDT = {
+ {PC_OPCODE, NULL, NULL, 0, NULL,
+ // genericAnalyze,
+ genericDestruct,
+ genericPrint},
+ POC_CLRWDT,
+ "CLRWDT",
+ NULL, // from branch
+ NULL, // to branch
+ NULL, // label
+ NULL, // operand
+ NULL, // flow block
+ NULL, // C source
+ 0, // num ops
+ 0,0, // dest, bit instruction
+ 0,0, // branch, skip
+ POC_NOP,
+ PCC_NONE, // inCond
+ PCC_NONE // outCond
+};
+
pCodeInstruction pciDECF = {
{PC_OPCODE, NULL, NULL, 0, NULL,
// genericAnalyze,
}
-/*-----------------------------------------------------------------*/
-/*-----------------------------------------------------------------*/
+/*-----------------------------------------------------------------*
+ * void LinkFlow(pBlock *pb)
+ *
+ * In BuildFlow, the PIC code has been partitioned into contiguous
+ * non-branching segments. In LinkFlow, we determine the execution
+ * order of these segments. For example, if one of the segments ends
+ * with a skip, then we know that there are two possible flow segments
+ * to which control may be passed.
+ *-----------------------------------------------------------------*/
void LinkFlow(pBlock *pb)
{
pCode *pc=NULL;
}
}
+/*-----------------------------------------------------------------*/
+/*-----------------------------------------------------------------*/
/*-----------------------------------------------------------------*/
/*-----------------------------------------------------------------*/
{
pBlock *pb;
+ if(!picIsInitialized()) {
+ fprintf(stderr,"Temporary ERROR: at the moment you have to use\n");
+ fprintf(stderr,"an include file create by inc2h.pl. See SDCC source:\n");
+ fprintf(stderr,"support/scripts/inc2h.pl\n");
+ fprintf(stderr,"this is a nuisance bug that will be fixed shortly\n");
+
+ exit(1);
+ }
+
/* Phase x - Flow Analysis - Used Banks
*
* In this phase, the individual flow blocks are examined