/* Hardcoded flags to change the behavior of the PIC port */
static int peepOptimizing = 1; /* run the peephole optimizer if nonzero */
static int functionInlining = 1; /* inline functions if nonzero */
+int debug_verbose = 0; /* Set true to inundate .asm file */
-static int GpCodeSequenceNumber = 1;
+// static int GpCodeSequenceNumber = 1;
int GpcFlowSeq = 1;
extern void RemoveUnusedRegisters(void);
+extern void RegsUnMapLiveRanges(void);
extern void BuildFlowTree(pBlock *pb);
-extern void pCodeRegOptimizeRegUsage(void);
+extern void pCodeRegOptimizeRegUsage(int level);
+extern int picIsInitialized(void);
/****************************************************************/
/* Forward declarations */
static void pCodePrintFunction(FILE *of, pCode *pc);
static void pCodeOpPrint(FILE *of, pCodeOp *pcop);
static char *get_op_from_instruction( pCodeInstruction *pcc);
-char *get_op( pCodeOp *pcop,char *buff,int buf_size);
+char *get_op( pCodeOp *pcop,char *buff,size_t buf_size);
int pCodePeepMatchLine(pCodePeep *peepBlock, pCode *pcs, pCode *pcd);
int pCodePeepMatchRule(pCode *pc);
void pBlockStats(FILE *of, pBlock *pb);
2, // num ops
1,0, // dest, bit instruction
0,0, // branch, skip
+ 0, // literal operand
POC_NOP,
(PCC_W | PCC_REGISTER), // inCond
(PCC_REGISTER | PCC_Z) // outCond
2, // num ops
0,0, // dest, bit instruction
0,0, // branch, skip
+ 0, // literal operand
POC_NOP,
(PCC_W | PCC_REGISTER), // inCond
(PCC_W | PCC_Z) // outCond
1, // num ops
0,0, // dest, bit instruction
0,0, // branch, skip
+ 1, // literal operand
POC_NOP,
- PCC_W, // inCond
+ (PCC_W | PCC_LITERAL), // inCond
(PCC_W | PCC_Z | PCC_C | PCC_DC) // outCond
};
1, // num ops
0,0, // dest, bit instruction
0,0, // branch, skip
+ 1, // literal operand
POC_NOP,
- PCC_W, // inCond
+ (PCC_W | PCC_LITERAL), // inCond
(PCC_W | PCC_Z) // outCond
};
2, // num ops
1,0, // dest, bit instruction
0,0, // branch, skip
+ 0, // literal operand
POC_NOP,
(PCC_W | PCC_REGISTER), // inCond
(PCC_REGISTER | PCC_Z) // outCond
2, // num ops
0,0, // dest, bit instruction
0,0, // branch, skip
+ 0, // literal operand
POC_NOP,
(PCC_W | PCC_REGISTER), // inCond
(PCC_W | PCC_Z) // outCond
2, // num ops
1,1, // dest, bit instruction
0,0, // branch, skip
+ 0, // literal operand
POC_BSF,
- PCC_REGISTER, // inCond
+ (PCC_REGISTER | PCC_EXAMINE_PCOP), // inCond
PCC_REGISTER // outCond
};
2, // num ops
1,1, // dest, bit instruction
0,0, // branch, skip
+ 0, // literal operand
POC_BCF,
- PCC_REGISTER, // inCond
- PCC_REGISTER // outCond
+ (PCC_REGISTER | PCC_EXAMINE_PCOP), // inCond
+ (PCC_REGISTER | PCC_EXAMINE_PCOP) // outCond
};
pCodeInstruction pciBTFSC = {
2, // num ops
0,1, // dest, bit instruction
1,1, // branch, skip
+ 0, // literal operand
POC_BTFSS,
- PCC_REGISTER, // inCond
- PCC_NONE // outCond
+ (PCC_REGISTER | PCC_EXAMINE_PCOP), // inCond
+ PCC_EXAMINE_PCOP // outCond
};
pCodeInstruction pciBTFSS = {
2, // num ops
0,1, // dest, bit instruction
1,1, // branch, skip
+ 0, // literal operand
POC_BTFSC,
- PCC_REGISTER, // inCond
- PCC_NONE // outCond
+ (PCC_REGISTER | PCC_EXAMINE_PCOP), // inCond
+ PCC_EXAMINE_PCOP // outCond
};
pCodeInstruction pciCALL = {
1, // num ops
0,0, // dest, bit instruction
1,0, // branch, skip
+ 0, // literal operand
POC_NOP,
PCC_NONE, // inCond
PCC_NONE // outCond
2, // num ops
1,0, // dest, bit instruction
0,0, // branch, skip
+ 0, // literal operand
POC_NOP,
PCC_REGISTER, // inCond
PCC_REGISTER // outCond
2, // num ops
0,0, // dest, bit instruction
0,0, // branch, skip
+ 0, // literal operand
POC_NOP,
PCC_REGISTER, // inCond
PCC_W // outCond
1, // num ops
0,0, // dest, bit instruction
0,0, // branch, skip
+ 0, // literal operand
POC_NOP,
PCC_NONE, // inCond
PCC_REGISTER // outCond
0, // num ops
0,0, // dest, bit instruction
0,0, // branch, skip
+ 0, // literal operand
POC_NOP,
PCC_NONE, // inCond
PCC_W // outCond
};
+pCodeInstruction pciCLRWDT = {
+ {PC_OPCODE, NULL, NULL, 0, NULL,
+ // genericAnalyze,
+ genericDestruct,
+ genericPrint},
+ POC_CLRWDT,
+ "CLRWDT",
+ NULL, // from branch
+ NULL, // to branch
+ NULL, // label
+ NULL, // operand
+ NULL, // flow block
+ NULL, // C source
+ 0, // num ops
+ 0,0, // dest, bit instruction
+ 0,0, // branch, skip
+ 0, // literal operand
+ POC_NOP,
+ PCC_NONE, // inCond
+ PCC_NONE // outCond
+};
+
pCodeInstruction pciDECF = {
{PC_OPCODE, NULL, NULL, 0, NULL,
// genericAnalyze,
2, // num ops
1,0, // dest, bit instruction
0,0, // branch, skip
+ 0, // literal operand
POC_NOP,
PCC_REGISTER, // inCond
PCC_REGISTER // outCond
2, // num ops
0,0, // dest, bit instruction
0,0, // branch, skip
+ 0, // literal operand
POC_NOP,
PCC_REGISTER, // inCond
PCC_W // outCond
2, // num ops
1,0, // dest, bit instruction
1,1, // branch, skip
+ 0, // literal operand
POC_NOP,
PCC_REGISTER, // inCond
PCC_REGISTER // outCond
2, // num ops
0,0, // dest, bit instruction
1,1, // branch, skip
+ 0, // literal operand
POC_NOP,
PCC_REGISTER, // inCond
PCC_W // outCond
1, // num ops
0,0, // dest, bit instruction
1,0, // branch, skip
+ 0, // literal operand
POC_NOP,
PCC_NONE, // inCond
PCC_NONE // outCond
2, // num ops
1,0, // dest, bit instruction
0,0, // branch, skip
+ 0, // literal operand
POC_NOP,
PCC_REGISTER, // inCond
PCC_REGISTER // outCond
2, // num ops
0,0, // dest, bit instruction
0,0, // branch, skip
+ 0, // literal operand
POC_NOP,
PCC_REGISTER, // inCond
PCC_W // outCond
2, // num ops
1,0, // dest, bit instruction
1,1, // branch, skip
+ 0, // literal operand
POC_NOP,
PCC_REGISTER, // inCond
PCC_REGISTER // outCond
2, // num ops
0,0, // dest, bit instruction
1,1, // branch, skip
+ 0, // literal operand
POC_NOP,
PCC_REGISTER, // inCond
PCC_W // outCond
2, // num ops
1,0, // dest, bit instruction
0,0, // branch, skip
+ 0, // literal operand
POC_NOP,
(PCC_W | PCC_REGISTER), // inCond
(PCC_REGISTER | PCC_Z) // outCond
2, // num ops
0,0, // dest, bit instruction
0,0, // branch, skip
+ 0, // literal operand
POC_NOP,
(PCC_W | PCC_REGISTER), // inCond
(PCC_W | PCC_Z) // outCond
1, // num ops
0,0, // dest, bit instruction
0,0, // branch, skip
+ 1, // literal operand
POC_NOP,
- PCC_W, // inCond
+ (PCC_W | PCC_LITERAL), // inCond
(PCC_W | PCC_Z) // outCond
};
2, // num ops
1,0, // dest, bit instruction
0,0, // branch, skip
+ 0, // literal operand
POC_NOP,
PCC_REGISTER, // inCond
PCC_Z // outCond
2, // num ops
0,0, // dest, bit instruction
0,0, // branch, skip
+ 0, // literal operand
POC_NOP,
PCC_REGISTER, // inCond
(PCC_W | PCC_Z) // outCond
1, // num ops
0,0, // dest, bit instruction
0,0, // branch, skip
+ 0, // literal operand
POC_NOP,
PCC_W, // inCond
PCC_REGISTER // outCond
pCodeInstruction pciMOVLW = {
{PC_OPCODE, NULL, NULL, 0, NULL,
- // genericAnalyze,
genericDestruct,
genericPrint},
POC_MOVLW,
1, // num ops
0,0, // dest, bit instruction
0,0, // branch, skip
+ 1, // literal operand
POC_NOP,
- PCC_NONE, // inCond
+ (PCC_NONE | PCC_LITERAL), // inCond
PCC_W // outCond
};
0, // num ops
0,0, // dest, bit instruction
0,0, // branch, skip
+ 0, // literal operand
POC_NOP,
PCC_NONE, // inCond
PCC_NONE // outCond
0, // num ops
0,0, // dest, bit instruction
1,0, // branch, skip
+ 0, // literal operand
POC_NOP,
PCC_NONE, // inCond
PCC_NONE // outCond (not true... affects the GIE bit too)
1, // num ops
0,0, // dest, bit instruction
1,0, // branch, skip
+ 1, // literal operand
POC_NOP,
- PCC_NONE, // inCond
+ PCC_LITERAL, // inCond
PCC_W // outCond
};
0, // num ops
0,0, // dest, bit instruction
1,0, // branch, skip
+ 0, // literal operand
POC_NOP,
PCC_NONE, // inCond
PCC_NONE // outCond
2, // num ops
1,0, // dest, bit instruction
0,0, // branch, skip
+ 0, // literal operand
POC_NOP,
(PCC_C | PCC_REGISTER), // inCond
(PCC_REGISTER | PCC_Z | PCC_C | PCC_DC) // outCond
2, // num ops
0,0, // dest, bit instruction
0,0, // branch, skip
+ 0, // literal operand
POC_NOP,
(PCC_C | PCC_REGISTER), // inCond
(PCC_W | PCC_Z | PCC_C | PCC_DC) // outCond
2, // num ops
1,0, // dest, bit instruction
0,0, // branch, skip
+ 0, // literal operand
POC_NOP,
(PCC_C | PCC_REGISTER), // inCond
(PCC_REGISTER | PCC_Z | PCC_C | PCC_DC) // outCond
2, // num ops
0,0, // dest, bit instruction
0,0, // branch, skip
+ 0, // literal operand
POC_NOP,
(PCC_C | PCC_REGISTER), // inCond
(PCC_W | PCC_Z | PCC_C | PCC_DC) // outCond
2, // num ops
1,0, // dest, bit instruction
0,0, // branch, skip
+ 0, // literal operand
POC_NOP,
(PCC_W | PCC_REGISTER), // inCond
(PCC_REGISTER | PCC_Z) // outCond
2, // num ops
0,0, // dest, bit instruction
0,0, // branch, skip
+ 0, // literal operand
POC_NOP,
(PCC_W | PCC_REGISTER), // inCond
(PCC_W | PCC_Z) // outCond
1, // num ops
0,0, // dest, bit instruction
0,0, // branch, skip
+ 1, // literal operand
POC_NOP,
- PCC_W, // inCond
+ (PCC_W | PCC_LITERAL), // inCond
(PCC_W | PCC_Z | PCC_C | PCC_DC) // outCond
};
2, // num ops
1,0, // dest, bit instruction
0,0, // branch, skip
+ 0, // literal operand
POC_NOP,
(PCC_REGISTER), // inCond
(PCC_REGISTER) // outCond
2, // num ops
0,0, // dest, bit instruction
0,0, // branch, skip
+ 0, // literal operand
POC_NOP,
(PCC_REGISTER), // inCond
(PCC_W) // outCond
1, // num ops
0,0, // dest, bit instruction
0,0, // branch, skip
+ 0, // literal operand
POC_NOP,
PCC_NONE, // inCond
PCC_REGISTER // outCond
2, // num ops
1,0, // dest, bit instruction
0,0, // branch, skip
+ 0, // literal operand
POC_NOP,
(PCC_W | PCC_REGISTER), // inCond
(PCC_REGISTER | PCC_Z) // outCond
2, // num ops
0,0, // dest, bit instruction
0,0, // branch, skip
+ 0, // literal operand
POC_NOP,
(PCC_W | PCC_REGISTER), // inCond
(PCC_W | PCC_Z) // outCond
1, // num ops
0,0, // dest, bit instruction
0,0, // branch, skip
+ 1, // literal operand
POC_NOP,
- PCC_W, // inCond
+ (PCC_W | PCC_LITERAL), // inCond
(PCC_W | PCC_Z | PCC_C | PCC_DC) // outCond
};
#define MAX_PIC14MNEMONICS 100
pCodeInstruction *pic14Mnemonics[MAX_PIC14MNEMONICS];
-/* This definition needs to be part of configure.in */
-// #define USE_VSNPRINTF
-#ifdef USE_VSNPRINTF
+#ifdef HAVE_VSNPRINTF
// Alas, vsnprintf is not ANSI standard, and does not exist
// on Solaris (and probably other non-Gnu flavored Unixes).
len = strlen(*str);
if(len > *size) {
fprintf(stderr,"WARNING, it looks like %s has overflowed\n",__FUNCTION__);
- fprintf(stderr,"len = %d is > str size %d\n",len,*size);
+ fprintf(stderr,"len = %d is > str size %d\n",len,(int)*size);
}
*str += len;
}
-#else // USE_VSNPRINTF
+#else // HAVE_VSNPRINTF
// This version is *not* safe, despite the name.
}
-#endif // USE_VSNPRINTF
+#endif // HAVE_VSNPRINTF
extern void initStack(int base_address, int size);
void pCodeInitRegisters(void)
{
+ static int initialized=0;
+
+ if(initialized)
+ return;
+ initialized = 1;
initStack(0xfff, 8);
init_pic(port->processor);
pic14Mnemonics[POC_COMFW] = &pciCOMFW;
pic14Mnemonics[POC_CLRF] = &pciCLRF;
pic14Mnemonics[POC_CLRW] = &pciCLRW;
+ pic14Mnemonics[POC_CLRWDT] = &pciCLRWDT;
pic14Mnemonics[POC_DECF] = &pciDECF;
pic14Mnemonics[POC_DECFW] = &pciDECFW;
pic14Mnemonics[POC_DECFSZ] = &pciDECFSZ;
while(pci) {
if(STRCASECMP(pci->mnemonic, mnem) == 0) {
- if((pci->num_ops <= 1) || (pci->isModReg == dest))
+ if((pci->num_ops <= 1) || (pci->isModReg == dest) || (pci->isBitInst))
return(pci->op);
}
if(getpBlock_dbName(pb) == dbName) {
pBlockStats(of,pb);
printpBlock(of,pb);
+ fprintf (of, "\n");
}
}
char buffer[100];
/* create the file name */
- strcpy(buffer,srcFileName);
+ strcpy(buffer,dstFileName);
strcat(buffer,".p");
if( !(pFile = fopen(buffer, "w" ))) {
memcpy(pci, pic14Mnemonics[op], sizeof(pCodeInstruction));
pci->pcop = pcop;
- if(pci->inCond == PCC_EXAMINE_PCOP)
- pci->inCond = RegCond(pcop);
+ if(pci->inCond & PCC_EXAMINE_PCOP)
+ pci->inCond |= RegCond(pcop);
- if(pci->outCond == PCC_EXAMINE_PCOP)
- pci->outCond = RegCond(pcop);
+ if(pci->outCond & PCC_EXAMINE_PCOP)
+ pci->outCond |= RegCond(pcop);
pci->pc.prev = pci->pc.next = NULL;
return (pCode *)pci;
/*-----------------------------------------------------------------*/
/* newpCodeFlow */
/*-----------------------------------------------------------------*/
-
void destructpCodeFlow(pCode *pc)
{
if(!pc || !isPCFL(pc))
return;
- if(PCFL(pc)->uses)
- free(PCFL(pc)->uses);
/*
if(PCFL(pc)->from)
if(PCFL(pc)->to)
*/
+ unlinkpCode(pc);
+
+ deleteSet(&PCFL(pc)->registers);
+ deleteSet(&PCFL(pc)->from);
+ deleteSet(&PCFL(pc)->to);
free(pc);
+
}
pCode *newpCodeFlow(void )
pcflow->pc.type = PC_FLOW;
pcflow->pc.prev = pcflow->pc.next = NULL;
- //pcflow->pc.from = pcflow->pc.to = pcflow->pc.label = NULL;
pcflow->pc.pb = NULL;
// pcflow->pc.analyze = genericAnalyze;
pcflow->pc.seq = GpcFlowSeq++;
- pcflow->nuses = 7;
- pcflow->uses = Safe_calloc(pcflow->nuses, sizeof(set *));
-
pcflow->from = pcflow->to = NULL;
pcflow->inCond = PCC_NONE;
if(s)
pcl->label = Safe_strdup(s);
-
+ //fprintf(stderr,"newpCodeLabel: key=%d, name=%s\n",key, ((s)?s:""));
return ( (pCode *)pcl);
}
((pCodeOpLabel *)pcop)->key = key;
+ //fprintf(stderr,"newpCodeOpLabel: key=%d, name=%s\n",key,((s)?s:""));
return pcop;
}
/*-----------------------------------------------------------------*/
/*-----------------------------------------------------------------*/
-pCodeOp *newpCodeOpImmd(char *name, int offset, int index, int code_space)
+pCodeOp *newpCodeOpImmd(char *name, int offset, int index, int code_space, int is_func)
{
pCodeOp *pcop;
pcop = Safe_calloc(1,sizeof(pCodeOpImmd) );
pcop->type = PO_IMMEDIATE;
if(name) {
+ regs *r = NULL;
pcop->name = Safe_strdup(name);
+
+ if(!is_func)
+ r = dirregWithName(name);
+
+ PCOI(pcop)->r = r;
+ if(r) {
+ //fprintf(stderr, " newpCodeOpImmd reg %s exists\n",name);
+ PCOI(pcop)->rIdx = r->rIdx;
+ } else {
+ //fprintf(stderr, " newpCodeOpImmd reg %s doesn't exist\n",name);
+ PCOI(pcop)->rIdx = -1;
+ }
//fprintf(stderr,"%s %s %d\n",__FUNCTION__,name,offset);
} else {
pcop->name = NULL;
}
-
PCOI(pcop)->index = index;
PCOI(pcop)->offset = offset;
PCOI(pcop)->_const = code_space;
+ PCOI(pcop)->_function = is_func;
return pcop;
}
PCORB(pcop)->bit = bit;
PCORB(pcop)->inBitSpace = inBitSpace;
+ /* pCodeOpBit is derived from pCodeOpReg. We need to init this too */
+ PCOR(pcop)->r = NULL;
+ PCOR(pcop)->rIdx = 0;
return pcop;
}
if(PCOR(pcop)->r)
PCOR(pcop)->rIdx = PCOR(pcop)->r->rIdx;
- //fprintf(stderr, "newpcodeOpReg - rIdx = %d\n", PCOR(pcop)->r->rIdx);
}
pcop->type = PCOR(pcop)->r->pc_type;
pcop = newpCodeOpReg(-1);
break;
+ case PO_GPR_POINTER:
+ case PO_GPR_REGISTER:
+ if(name)
+ pcop = newpCodeOpRegFromStr(name);
+ else
+ pcop = newpCodeOpReg(-1);
+ break;
+
default:
pcop = Safe_calloc(1,sizeof(pCodeOp) );
pcop->type = type;
/*-----------------------------------------------------------------*/
void addpCode2pBlock(pBlock *pb, pCode *pc)
{
+
+ if(!pc)
+ return;
+
if(!pb->pcHead) {
/* If this is the first pcode to be added to a block that
* was initialized with a NULL pcode, then go ahead and
* make this pcode the head and tail */
pb->pcHead = pb->pcTail = pc;
} else {
+ // if(pb->pcTail)
pb->pcTail->next = pc;
+
pc->prev = pb->pcTail;
- //pc->next = NULL;
pc->pb = pb;
+
pb->pcTail = pc;
}
}
/*-----------------------------------------------------------------*/
/*-----------------------------------------------------------------*/
-char *get_op(pCodeOp *pcop,char *buffer, int size)
+char *get_op(pCodeOp *pcop,char *buffer, size_t size)
{
regs *r;
static char b[50];
SAFE_snprintf(&buffer,&size,"%s",PCOR(pcop)->r->name);
return buffer;
}
- return PCOR(pcop)->r->name;
+ //return PCOR(pcop)->r->name;
+ return pcop->name;
break;
case PO_GPR_TEMP:
r = pic14_regWithIdx(PCOR(pcop)->r->rIdx);
if(PCOI(pcop)->_const) {
if( PCOI(pcop)->offset && PCOI(pcop)->offset<4) {
- SAFE_snprintf(&s,&size,"(((%s+%d) >> %d)&0xff)",
- pcop->name,
- PCOI(pcop)->index,
- 8 * PCOI(pcop)->offset );
+ switch(PCOI(pcop)->offset) {
+ case 0:
+ SAFE_snprintf(&s,&size,"low %s",pcop->name);
+ break;
+ case 1:
+ SAFE_snprintf(&s,&size,"high %s",pcop->name);
+ break;
+ default:
+ SAFE_snprintf(&s,&size,"(((%s+%d) >> %d)&0xff)",
+ pcop->name,
+ PCOI(pcop)->index,
+ 8 * PCOI(pcop)->offset );
+ }
} else
SAFE_snprintf(&s,&size,"LOW(%s+%d)",pcop->name,PCOI(pcop)->index);
} else {
SAFE_snprintf(&s,&size,"(%s + %d)",
pcop->name,
PCOI(pcop)->index );
- } else
- SAFE_snprintf(&s,&size,"%s",pcop->name);
+ } else {
+ switch(PCOI(pcop)->offset) {
+ case 0:
+ SAFE_snprintf(&s,&size,"%s",pcop->name);
+ break;
+ case 1:
+ SAFE_snprintf(&s,&size,"high %s",pcop->name);
+ break;
+ default:
+ SAFE_snprintf(&s,&size,"(%s >> %d)&0xff",pcop->name, 8*PCOI(pcop)->offset);
+ }
+ }
}
return buffer;
if(pcc )
return get_op(pcc->pcop,NULL,0);
-
+
+ /* gcc 3.2: warning: concatenation of string literals with __FUNCTION__ is deprecated
return ("ERROR Null: "__FUNCTION__);
+ */
+ return ("ERROR Null: get_op_from_instruction");
}
/*-----------------------------------------------------------------*/
/*-----------------------------------------------------------------*/
-char *pCode2str(char *str, int size, pCode *pc)
+char *pCode2str(char *str, size_t size, pCode *pc)
{
char *s = str;
fprintf(of,"%s",str);
/* Debug */
- fprintf(of, "\t;key=%03x",pc->seq);
- if(PCI(pc)->pcflow)
- fprintf(of,",flow seq=%03x",PCI(pc)->pcflow->pc.seq);
+ if(debug_verbose) {
+ fprintf(of, "\t;key=%03x",pc->seq);
+ if(PCI(pc)->pcflow)
+ fprintf(of,",flow seq=%03x",PCI(pc)->pcflow->pc.seq);
+ }
}
#if 0
{
break;
case PC_FLOW:
- fprintf(of,";<>Start of new flow, seq=%d\n",pc->seq);
+ if(debug_verbose) {
+ fprintf(of,";<>Start of new flow, seq=0x%x",pc->seq);
+ if(PCFL(pc)->ancestor)
+ fprintf(of," ancestor = 0x%x", PCODE(PCFL(pc)->ancestor)->seq);
+ fprintf(of,"\n");
+
+ }
break;
case PC_CSOURCE:
/*-----------------------------------------------------------------*/
/*-----------------------------------------------------------------*/
-static pBranch * pBranchAppend(pBranch *h, pBranch *n)
+pBranch * pBranchAppend(pBranch *h, pBranch *n)
{
pBranch *b;
if(!h)
return n;
+ if(h == n)
+ return n;
+
b = h;
while(b->next)
b = b->next;
/*-----------------------------------------------------------------*/
regs * getRegFromInstruction(pCode *pc)
{
+
if(!pc ||
!isPCI(pc) ||
!PCI(pc)->pcop ||
switch(PCI(pc)->pcop->type) {
case PO_INDF:
case PO_FSR:
- return typeRegWithIdx (PCOR(PCI(pc)->pcop)->rIdx, REG_SFR, 0);
+ return PCOR(PCI(pc)->pcop)->r;
+
+ // return typeRegWithIdx (PCOR(PCI(pc)->pcop)->rIdx, REG_SFR, 0);
case PO_BIT:
case PO_GPR_TEMP:
return PCOR(PCI(pc)->pcop)->r;
case PO_IMMEDIATE:
+ if(PCOI(PCI(pc)->pcop)->r)
+ return (PCOI(PCI(pc)->pcop)->r);
+
//fprintf(stderr, "getRegFromInstruction - immediate\n");
- return NULL; // PCOR(PCI(pc)->pcop)->r;
+ return dirregWithName(PCI(pc)->pcop->name);
+ //return NULL; // PCOR(PCI(pc)->pcop)->r;
case PO_GPR_BIT:
return PCOR(PCI(pc)->pcop)->r;
void InsertpFlow(pCode *pc, pCode **pflow)
{
- PCFL(*pflow)->end = pc;
+ if(*pflow)
+ PCFL(*pflow)->end = pc;
if(!pc || !pc->next)
return;
{
pCode *pc;
pCode *last_pci=NULL;
- pCode *pflow;
+ pCode *pflow=NULL;
int seq = 0;
if(!pb)
//fprintf (stderr,"build flow start seq %d ",GpcFlowSeq);
/* Insert a pCodeFlow object at the beginning of a pBlock */
- pflow = newpCodeFlow(); /* Create a new Flow object */
- pflow->next = pb->pcHead; /* Make the current head the next object */
- pb->pcHead->prev = pflow; /* let the current head point back to the flow object */
- pb->pcHead = pflow; /* Make the Flow object the head */
- pflow->pb = pb;
+ InsertpFlow(pb->pcHead, &pflow);
+
+ //pflow = newpCodeFlow(); /* Create a new Flow object */
+ //pflow->next = pb->pcHead; /* Make the current head the next object */
+ //pb->pcHead->prev = pflow; /* let the current head point back to the flow object */
+ //pb->pcHead = pflow; /* Make the Flow object the head */
+ //pflow->pb = pb;
for( pc = findNextInstruction(pb->pcHead);
pc != NULL;
InsertpFlow(pc, &pflow);
seq = 0;
- } else if (checkLabel(pc)) { //(PCI_HAS_LABEL(pc)) {
+ } else if (checkLabel(pc)) {
/* This instruction marks the beginning of a
* new flow segment */
pc->seq = 0;
- seq = 1;
- InsertpFlow(findPrevInstruction(pc->prev), &pflow);
+ seq = 1;
+
+ /* If the previous pCode is not a flow object, then
+ * insert a new flow object. (This check prevents
+ * two consecutive flow objects from being insert in
+ * the case where a skip instruction preceeds an
+ * instruction containing a label.) */
+
+ if(last_pci && (PCI(last_pci)->pcflow == PCFL(pflow)))
+ InsertpFlow(findPrevInstruction(pc->prev), &pflow);
PCI(pc)->pcflow = PCFL(pflow);
}
//fprintf (stderr,",end seq %d",GpcFlowSeq);
- PCFL(pflow)->end = pb->pcTail;
+ if(pflow)
+ PCFL(pflow)->end = pb->pcTail;
}
/*-------------------------------------------------------------------*/
/*-----------------------------------------------------------------*/
void unBuildFlow(pBlock *pb)
{
- pCode *pc;
+ pCode *pc,*pcnext;
if(!pb)
return;
pc = pb->pcHead;
+
while(pc) {
- pCode *pcn = pc->next;
+ pcnext = pc->next;
if(isPCI(pc)) {
+
pc->seq = 0;
- PCI(pc)->pcflow = NULL;
- pc = pcn;
- } else if(isPCFL(pc)) {
- unlinkpCode(pc);
+ if(PCI(pc)->pcflow) {
+ //free(PCI(pc)->pcflow);
+ PCI(pc)->pcflow = NULL;
+ }
+
+ } else if(isPCFL(pc) )
pc->destruct(pc);
- } else
- pc = pcn;
+ pc = pcnext;
}
+
}
/*-----------------------------------------------------------------*/
}
-/*-----------------------------------------------------------------*/
-/*-----------------------------------------------------------------*/
+/*-----------------------------------------------------------------*
+ * void LinkFlow(pBlock *pb)
+ *
+ * In BuildFlow, the PIC code has been partitioned into contiguous
+ * non-branching segments. In LinkFlow, we determine the execution
+ * order of these segments. For example, if one of the segments ends
+ * with a skip, then we know that there are two possible flow segments
+ * to which control may be passed.
+ *-----------------------------------------------------------------*/
void LinkFlow(pBlock *pb)
{
pCode *pc=NULL;
//pc->print(stderr,pc);
if(!(pcol && isPCOLAB(pcol))) {
- if((PCI(pc)->op != POC_RETURN) && (PCI(pc)->op != POC_CALL)) {
+ if((PCI(pc)->op != POC_RETLW) && (PCI(pc)->op != POC_RETURN) && (PCI(pc)->op != POC_CALL) && (PCI(pc)->op != POC_RETFIE) ) {
pc->print(stderr,pc);
fprintf(stderr, "ERROR: %s, branch instruction doesn't have label\n",__FUNCTION__);
}
if( (pct = findLabelinpBlock(pb,pcol)) != NULL)
LinkFlow_pCode(PCI(pc),PCI(pct));
else
- fprintf(stderr, "ERROR: %s, couldn't find label\n",__FUNCTION__);
+ fprintf(stderr, "ERROR: %s, couldn't find label. key=%d,lab=%s\n",
+ __FUNCTION__,pcol->key,((PCOP(pcol)->name)?PCOP(pcol)->name:"-"));
+ //fprintf(stderr,"newpCodeOpLabel: key=%d, name=%s\n",key,((s)?s:""));
continue;
}
}
}
+/*-----------------------------------------------------------------*/
+/*-----------------------------------------------------------------*/
/*-----------------------------------------------------------------*/
/*-----------------------------------------------------------------*/
/*-----------------------------------------------------------------*/
/*-----------------------------------------------------------------*/
-void insertBankSwitch(pCode *pc, int Set_Clear, int RP_BankBit)
+void insertBankSwitch(int position, pCode *pc, int Set_Clear, int RP_BankBit)
{
pCode *new_pc;
new_pc = newpCode((Set_Clear ? POC_BSF : POC_BCF),
popCopyGPR2Bit(PCOP(&pc_status),RP_BankBit));
- pCodeInsertAfter(pc->prev, new_pc);
+ if(position) {
+ /* insert the bank switch after this pc instruction */
+ pCode *pcnext = findNextInstruction(pc);
+ pCodeInsertAfter(pc, new_pc);
+ if(pcnext)
+ pc = pcnext;
+
+ } else
+ pCodeInsertAfter(pc->prev, new_pc);
/* Move the label, if there is one */
while(isPCinFlow(pc,PCODE(pcfl))) {
-
reg = getRegFromInstruction(pc);
#if 0
if(reg) {
}
#endif
- if(reg && REG_BANK(reg)!=cur_bank) {
+ if( ( (reg && REG_BANK(reg)!=cur_bank) ||
+ ((PCI(pc)->op == POC_CALL) && (cur_bank != 0) ) ) &&
+ (!isPCI_LIT(pc)) ){
+
/* Examine the instruction before this one to make sure it is
* not a skip type instruction */
pcprev = findPrevpCode(pc->prev, PC_OPCODE);
+
if(!pcprev || (pcprev && !isPCI_SKIP(pcprev))) {
- int b = cur_bank ^ REG_BANK(reg);
+ int b;
+ int reg_bank;
+
+ reg_bank = (reg) ? REG_BANK(reg) : 0;
+
+ b = cur_bank ^ reg_bank;
//fprintf(stderr, "Cool! can switch banks\n");
- cur_bank = REG_BANK(reg);
+ cur_bank = reg_bank;
switch(b & 3) {
case 0:
break;
case 1:
- insertBankSwitch(pc, cur_bank&1, PIC_RP0_BIT);
+ insertBankSwitch(0, pc, cur_bank&1, PIC_RP0_BIT);
break;
case 2:
- insertBankSwitch(pc, cur_bank&2, PIC_RP1_BIT);
- insertBankSwitch(pc, cur_bank&2, PIC_RP1_BIT);
+ insertBankSwitch(0, pc, cur_bank&2, PIC_RP1_BIT);
+ insertBankSwitch(0, pc, cur_bank&2, PIC_RP1_BIT);
break;
case 3:
if(cur_bank & 3) {
- insertBankSwitch(pc, cur_bank&1, PIC_RP0_BIT);
- insertBankSwitch(pc, cur_bank&2, PIC_RP1_BIT);
+ insertBankSwitch(0, pc, cur_bank&1, PIC_RP0_BIT);
+ insertBankSwitch(0, pc, cur_bank&2, PIC_RP1_BIT);
} else
- insertBankSwitch(pc, -1, -1);
+ insertBankSwitch(0, pc, -1, -1);
break;
- /*
- new_pc = newpCode(((cur_bank&1) ? POC_BSF : POC_BCF),
- popCopyGPR2Bit(PCOP(&pc_status),PIC_RP0_BIT));
- pCodeInsertAfter(pc->prev, new_pc);
- if(PCI(pc)->label) {
- PCI(new_pc)->label = PCI(pc)->label;
- PCI(pc)->label = NULL;
- }
- */
- /*
- new_pc = newpCode(((cur_bank&1) ? POC_BCF : POC_BSF),
- popCopyGPR2Bit(PCOP(&pc_status),PIC_RP0_BIT));
- pCodeInsertAfter(pc, new_pc);
- */
}
*/
pc = findNextInstruction(pb->pcHead);
+ if(!pc)
+ return 0;
+
pcprev = pc->prev;
do {
void exchangeLabels(pCodeLabel *pcl, pCode *pc)
{
+ char *s=NULL;
+
if(isPCI(pc) &&
(PCI(pc)->pcop) &&
(PCI(pc)->pcop->type == PO_LABEL)) {
if(pcol->pcop.name)
free(pcol->pcop.name);
- sprintf(buffer,"_%05d_DS_",pcl->key);
-
- pcol->pcop.name = Safe_strdup(buffer);
+ /* If the key is negative, then we (probably) have a label to
+ * a function and the name is already defined */
+
+ if(pcl->key>0)
+ sprintf(s=buffer,"_%05d_DS_",pcl->key);
+ else
+ s = pcl->label;
+
+ //sprintf(buffer,"_%05d_DS_",pcl->key);
+ if(!s) {
+ fprintf(stderr, "ERROR %s:%d function label is null\n",__FUNCTION__,__LINE__);
+ }
+ pcol->pcop.name = Safe_strdup(s);
pcol->key = pcl->key;
//pc->print(stderr,pc);
/* Now loop through the pBlock and merge the labels with the opcodes */
- for(pc = pb->pcHead; pc; pc = pc->next) {
+ pc = pb->pcHead;
+ // for(pc = pb->pcHead; pc; pc = pc->next) {
+
+ while(pc) {
+ pCode *pcn = pc->next;
if(pc->type == PC_LABEL) {
//fprintf(stderr,"Checking label key = %d\n",PCL(pc)->key);
if((pcnext = findNextInstruction(pc) )) {
- pCode *pcn = pc->next;
-
// Unlink the pCode label from it's pCode chain
unlinkpCode(pc);
pbr->pc = pc;
pbr->next = NULL;
-
PCI(pcnext)->label = pBranchAppend(PCI(pcnext)->label,pbr);
-
- pc = pcn;
} else {
fprintf(stderr, "WARNING: couldn't associate label %s with an instruction\n",PCL(pc)->label);
/* merge the source line symbolic info into the next instruction */
if((pcnext = findNextInstruction(pc) )) {
- pCode *pcn = pc->next;
-
// Unlink the pCode label from it's pCode chain
unlinkpCode(pc);
PCI(pcnext)->cline = PCCS(pc);
//fprintf(stderr, "merging CSRC\n");
//genericPrint(stderr,pcnext);
- pc = pcn;
}
}
-
+ pc = pcn;
}
pBlockRemoveUnusedLabels(pb);
{
pCode *pc=NULL;
pCode *pcprev=NULL;
- pCode *new_pc;
int cur_bank;
regs *reg;
- // return;
+
if(!pb)
return;
//genericPrint(stderr, pc);
reg = getRegFromInstruction(pc);
- #if 0
+#if 0
if(reg) {
fprintf(stderr, " %s ",reg->name);
- fprintf(stderr, "addr = 0x%03x, bank = %d\n",reg->address,REG_BANK(reg));
+ fprintf(stderr, "addr = 0x%03x, bank = %d, bit=%d\n",
+ reg->address,REG_BANK(reg),reg->isBitField);
}
- #endif
- if(reg && REG_BANK(reg)!=cur_bank) {
+#endif
+
+ if( ( (reg && REG_BANK(reg)!=cur_bank) ||
+ ((PCI(pc)->op == POC_CALL) && (cur_bank != 0) ) ) &&
+ (!isPCI_LIT(pc)) ){
+
+
/* Examine the instruction before this one to make sure it is
* not a skip type instruction */
pcprev = findPrevpCode(pc->prev, PC_OPCODE);
- if(!pcprev || (pcprev && !isPCI_SKIP(pcprev))) {
- int b = cur_bank ^ REG_BANK(reg);
- //fprintf(stderr, "Cool! can switch banks\n");
- cur_bank = REG_BANK(reg);
- if(b & 1) {
- new_pc = newpCode(((cur_bank&1) ? POC_BSF : POC_BCF),
- popCopyGPR2Bit(PCOP(&pc_status),PIC_RP0_BIT));
- pCodeInsertAfter(pc->prev, new_pc);
- if(PCI(pc)->label) {
- PCI(new_pc)->label = PCI(pc)->label;
- PCI(pc)->label = NULL;
- }
- /*
- new_pc = newpCode(((cur_bank&1) ? POC_BCF : POC_BSF),
- popCopyGPR2Bit(PCOP(&pc_status),PIC_RP0_BIT));
- pCodeInsertAfter(pc, new_pc);
- */
+ if(!pcprev || (pcprev && !isPCI_SKIP(pcprev))) {
+ int b;
+ int reg_bank;
+
+ reg_bank = (reg) ? REG_BANK(reg) : 0;
+
+ b = cur_bank ^ reg_bank;
+
+ cur_bank = reg_bank;
+ switch(b & 3) {
+ case 0:
+ break;
+ case 1:
+ insertBankSwitch(0, pc, cur_bank&1, PIC_RP0_BIT);
+ break;
+ case 2:
+ insertBankSwitch(0, pc, cur_bank&2, PIC_RP1_BIT);
+ insertBankSwitch(0, pc, cur_bank&2, PIC_RP1_BIT);
+ break;
+ case 3:
+ if(cur_bank & 3) {
+ insertBankSwitch(0, pc, cur_bank&1, PIC_RP0_BIT);
+ insertBankSwitch(0, pc, cur_bank&2, PIC_RP1_BIT);
+ } else
+ insertBankSwitch(0, pc, -1, -1);
+ break;
}
- } else {
+ }else {
//fprintf(stderr, "Bummer can't switch banks\n");
;
}
}
+
+ pcprev = pc;
+
}
- pcprev = pc;
pc = pc->next;
// } while(pc && !(isPCFL(pc)));
}while (pc);
- if(pcprev && cur_bank) {
- /* Brute force - make sure that we point to bank 0 at the
- * end of each flow block */
- new_pc = newpCode(POC_BCF,
- popCopyGPR2Bit(PCOP(&pc_status),PIC_RP0_BIT));
- pCodeInsertAfter(pcprev, new_pc);
- cur_bank = 0;
+ if(pcprev && cur_bank) {
+
+ int pos = 1; /* Assume that the bank swithc instruction(s)
+ * are inserted after this instruction */
+
+ if((PCI(pcprev)->op == POC_RETLW) ||
+ (PCI(pcprev)->op == POC_RETURN) ||
+ (PCI(pcprev)->op == POC_RETFIE)) {
+
+ /* oops, a RETURN - we need to switch banks *before* the RETURN */
+
+ pos = 0;
+
+ }
+
+ /* Brute force - make sure that we point to bank 0 at the
+ * end of each flow block */
+
+ switch(cur_bank & 3) {
+ case 0:
+ break;
+ case 1:
+ insertBankSwitch(pos, pcprev, 0, PIC_RP0_BIT);
+ break;
+ case 2:
+ insertBankSwitch(pos, pcprev, 0, PIC_RP1_BIT);
+ insertBankSwitch(pos, pcprev, 0, PIC_RP1_BIT);
+ break;
+ case 3:
+ insertBankSwitch(pos, pcprev, -1, -1);
+ break;
+
}
+/*
+ new_pc = newpCode(POC_BCF,
+ popCopyGPR2Bit(PCOP(&pc_status),PIC_RP0_BIT));
+ pCodeInsertAfter(pcprev, new_pc);
+*/
+ cur_bank = 0;
+ //fprintf(stderr, "Brute force switch\n");
+ }
}
+
+
+
+#if 0
+ if(reg && REG_BANK(reg)!=cur_bank) {
+ //fprintf(stderr,"need to switch banks\n");
+ /* Examine the instruction before this one to make sure it is
+ * not a skip type instruction */
+ pcprev = findPrevpCode(pc->prev, PC_OPCODE);
+ if(!pcprev || (pcprev && !isPCI_SKIP(pcprev))) {
+ int b = cur_bank ^ REG_BANK(reg);
+
+ cur_bank = REG_BANK(reg);
+
+ switch(b & 3) {
+ case 0:
+ break;
+ case 1:
+ insertBankSwitch(0, pc, cur_bank&1, PIC_RP0_BIT);
+ break;
+ case 2:
+ insertBankSwitch(0, pc, cur_bank&2, PIC_RP1_BIT);
+ insertBankSwitch(0, pc, cur_bank&2, PIC_RP1_BIT);
+ break;
+ case 3:
+ if(cur_bank & 3) {
+ insertBankSwitch(0, pc, cur_bank&1, PIC_RP0_BIT);
+ insertBankSwitch(0, pc, cur_bank&2, PIC_RP1_BIT);
+ } else
+ insertBankSwitch(0, pc, -1, -1);
+ break;
+
+ }
+#endif
+
+
+
+
void pBlockDestruct(pBlock *pb)
{
}
/*-----------------------------------------------------------------*/
-/* AnalyzeBanking - Called after the memory addresses have been */
-/* assigned to the registers. */
+/* AnalyzeFlow - Examine the flow of the code and optimize */
/* */
+/* level 0 == minimal optimization */
+/* optimize registers that are used only by two instructions */
+/* level 1 == maximal optimization */
+/* optimize by looking at pairs of instructions that use the */
+/* register. */
/*-----------------------------------------------------------------*/
-void AnalyzeBanking(void)
+
+void AnalyzeFlow(int level)
{
+ static int times_called=0;
pBlock *pb;
return;
+ /* if this is not the first time this function has been called,
+ then clean up old flow information */
+ if(times_called++) {
+ for(pb = the_pFile->pbHead; pb; pb = pb->next)
+ unBuildFlow(pb);
+
+ RegsUnMapLiveRanges();
+
+ }
+
+ GpcFlowSeq = 1;
+
/* Phase 2 - Flow Analysis - Register Banking
*
* In this phase, the individual flow blocks are examined
* In this phase, the individual flow blocks are examined
* to determine their order of excution.
*/
- /*
+
for(pb = the_pFile->pbHead; pb; pb = pb->next)
BuildFlowTree(pb);
- */
-
- /* Phase x - Flow Analysis - Used Banks
- *
- * In this phase, the individual flow blocks are examined
- * to determine the Register Banks they use
- */
- for(pb = the_pFile->pbHead; pb; pb = pb->next)
- BanksUsedFlow(pb);
/* Phase x - Flow Analysis - Used Banks
*
RemoveUnusedRegisters();
// for(pb = the_pFile->pbHead; pb; pb = pb->next)
- pCodeRegOptimizeRegUsage();
+ pCodeRegOptimizeRegUsage(level);
+
+ OptimizepCode('*');
+
/*
for(pb = the_pFile->pbHead; pb; pb = pb->next)
FillFlow(PCFL(pcflow));
}
}
+
/*
for(pb = the_pFile->pbHead; pb; pb = pb->next) {
pCode *pcflow;
*/
}
+/*-----------------------------------------------------------------*/
+/* AnalyzeBanking - Called after the memory addresses have been */
+/* assigned to the registers. */
+/* */
+/*-----------------------------------------------------------------*/
+
+void AnalyzeBanking(void)
+{
+ pBlock *pb;
+
+ if(!picIsInitialized()) {
+ fprintf(stderr,"Temporary ERROR: at the moment you have to use\n");
+ fprintf(stderr,"an include file create by inc2h.pl. See SDCC source:\n");
+ fprintf(stderr,"support/scripts/inc2h.pl\n");
+ fprintf(stderr,"this is a nuisance bug that will be fixed shortly\n");
+
+ exit(1);
+ }
+
+ /* Phase x - Flow Analysis - Used Banks
+ *
+ * In this phase, the individual flow blocks are examined
+ * to determine the Register Banks they use
+ */
+
+ AnalyzeFlow(0);
+ AnalyzeFlow(1);
+
+ for(pb = the_pFile->pbHead; pb; pb = pb->next)
+ BanksUsedFlow(pb);
+ for(pb = the_pFile->pbHead; pb; pb = pb->next)
+ FixRegisterBanking(pb);
+
+}
+
/*-----------------------------------------------------------------*/
/* buildCallTree - look at the flow and extract all of the calls */
/* */
projects / fw / sdcc / blobdiff