%3:
jnz %4
} by {
- ; Peephole 115 jump optimization
+ ; Peephole 115 jump optimization
cjne %1,%2,%3
sjmp %4
%3:
jc %1
}
-replace {
+replace {
mov r%1,@r%2
} by {
; Peephole 130 changed target address mode r%1 to ar%1
mov ar%1,@r%2
}
-replace {
+replace {
mov a,%1
subb a,#0x01
mov %2,a
mov %1,%2
} by {
; Peephole 131 optimized decrement (not caring for c)
- dec %1
- mov %2,%1
+ dec %1
+ mov %2,%1
}
replace {
mov %3,%4
} if notVolatile %1 %2
+// applies to f.e. bug-607243.c
+// also check notVolatile %3, as it will return FALSE if it's @r%1
+replace {
+ mov r%1,%2
+ mov ar%1,%3
+} by {
+ ; peephole 177.e removed redundant move
+ mov ar%1,%3
+} if notVolatile %2 %3
+
+replace {
+ mov ar%1,%2
+ mov r%1,%3
+} by {
+ ; peephole 177.f removed redundant move
+ mov r%1,%3
+} if notVolatile %2
+
replace {
mov a,%1
mov b,a
mov dptr,#(((%2)<<8) + %1)
}
+// applies to return 0.0; in f.e. sincosf.c
+replace {
+ mov dpl,#%1
+ clr a
+ mov dph,a
+} by {
+ ; Peephole 182.d used 16 bit load of dptr
+ mov dptr,#(%1&0x00ff)
+ clr a
+}
+
replace {
anl %1,#%2
anl %1,#%3
movc a,@a+dptr
mov %2,a
mov acc,b
- inc dptr
+ inc dptr
movc a,@a+dptr
mov %3,a
mov acc,b
inc dptr
}
-// char indexed access to: char code table[] = {4,3,2,1};
+// char indexed access to: char code table[] = {4,3,2,1};
replace {
add a,#%1
mov dpl,a
movc a,@a+dptr
}
-// char indexed access to: int code table[] = {4,3,2,1};
+// char indexed access to: int code table[] = {4,3,2,1};
replace {
mov b,#0x02
mul ab
cjne %5,%6,%3
sjmp %7
%3:
- sjmp %8
+ sjmp %8
} by {
; Peephole 197.a optimized misc jump sequence
jnz %8
mov a,%4
cjne %5,%6,%8
sjmp %7
-;%3:
+;%3:
} if labelRefCount %3 2
replace {
push %1
pop %1
} by {
- ; Peephole 211 removed redundant push %1 pop %1
-}
+ ; Peephole 211 removed redundant push %1 pop %1
+}
replace {
mov a,_bp
replace {
mov %1,#(( %2 + %3 >> 8 ) ^ 0x80)
} by {
- ; Peephole 213.b inserted fix
+ ; Peephole 213.b inserted fix
mov %1,#((%2 + %3) >> 8)
xrl %1,#0x80
}
mov %2,%10
mov %3,%11
mov %4,%12
-
+
mov %5,%13
mov %6,%14
mov %7,%15
mov %2,%10
mov %3,%11
mov %4,%12
-
+
mov %5,%13
mov %6,%14
mov %7,%15
mov %2,%6
mov %3,%7
mov %4,%8
-
+
mov %5,%1
mov %6,%2
mov %7,%3
replace {
mov %1,%5
mov %2,%6
-
+
mov %3,%7
mov %4,%8
} by {
mov %1,%5
mov %2,%6
-
+
mov %3,%7
mov %4,%8
; Peephole 238.c removed 2 redundant moves
mov %2,%5
mov %3,%6
; Peephole 238.d removed 3 redundant moves
-} if operandsNotSame6 %1 %2 %3 %4 %5 %6
+} if operandsNotSame6 %1 %2 %3 %4 %5 %6
// applies to f.e. ser_ir.asm
replace {
cjne r%6,#%7,%3
cjne r%8,#%9,%3
mov a,#0x01
- sjmp %10
-%3:
+ sjmp %10
+%3:
clr a
-%10:
+%10:
} by {
; Peephole 241.a optimized compare
clr a
inc a
%3:
%10:
-}
+}
// applies to f.e. time.c
replace {
cjne r%1,#%2,%3
cjne r%4,#%5,%3
mov a,#0x01
- sjmp %6
-%3:
+ sjmp %6
+%3:
clr a
-%6:
+%6:
} by {
; Peephole 241.b optimized compare
clr a
inc a
%3:
%6:
-}
+}
// applies to f.e. malloc.c
replace {
sjmp %4
%3:
clr a
-%4:
+%4:
} by {
; Peephole 241.c optimized compare
clr a
inc a
%3:
%4:
-}
+}
-// applies to f.e. j = (k!=0x1000);
+// applies to f.e. j = (k!=0x1000);
// with volatile idata long k;
replace {
cjne @r%1,#%2,%3
- inc r%1
+ inc r%1
cjne @r%1,#%4,%3
- inc r%1
+ inc r%1
cjne @r%1,#%5,%3
- inc r%1
+ inc r%1
cjne @r%1,#%6,%3
mov a,#0x01
- sjmp %7
-%3:
+ sjmp %7
+%3:
clr a
%7:
} by {
inc a
%3:
%7:
-}
+}
// applies to f.e. j = (k!=0x1000);
// with volatile idata int k;
replace {
cjne @r%1,#%2,%3
- inc r%1
+ inc r%1
cjne @r%1,#%4,%3
mov a,#0x01
- sjmp %7
-%3:
+ sjmp %7
+%3:
clr a
-%7:
+%7:
} by {
; Peephole 241.e optimized compare
clr a
inc a
%3:
%7:
-}
+}
// applies to f.e. vprintf.asm (--stack-auto)
replace {
sjmp %7
%3:
clr a
-%7:
+%7:
} by {
; Peephole 241.f optimized compare
clr a
inc a
%3:
%7:
-}
+}
// applies to f.e. scott-bool1.c
replace {
cjne %1,%2,%3
inc %4
%3:
- sjmp %5
+ sjmp %5
} by {
; Peephole 243 avoided branch to sjmp
cjne %1,%2,%5
inc %4
%3:
- sjmp %5
+ sjmp %5
} if labelInRange
// applies to f.e. simplefloat.c (saving 1 cycle)
rlc a
mov r%1,a
cjne a,#0x01,%2
-%2:
+%2:
clr a
rlc a
mov r%1,a
cpl c
clr a
rlc a
- mov r%1,a
+ mov r%1,a
} if labelRefCount %2 1
// this one will not be triggered if 245 is present
rlc a
mov r%1,a
cjne a,#0x01,%2
-%2:
+%2:
clr a
rlc a
mov r%1,a
rlc a
mov r%1,a
cjne a,#0x01,%2
-%2:
+%2:
clr a
rlc a
mov r%1,a
anl a,#%3
movx @dptr,a
} by {
- ; Peephole 246.a combined clr/clr
+ ; Peephole 246.a combined clr/clr
mov dptr,#%1
movx a,@dptr
anl a,#%2&%3
orl a,#%3
movx @dptr,a
} by {
- ; Peephole 246.b combined set/set
+ ; Peephole 246.b combined set/set
mov dptr,#%1
movx a,@dptr
orl a,#%2|%3
anl a,#%3
movx @dptr,a
} by {
- ; Peephole 246.c combined set/clr
+ ; Peephole 246.c combined set/clr
mov dptr,#%1
movx a,@dptr
orl a,#%2
orl a,#%3
movx @dptr,a
} by {
- ; Peephole 246.d combined clr/set
+ ; Peephole 246.d combined clr/set
mov dptr,#%1
movx a,@dptr
anl a,#%2
anl a,#%4
movx @dptr,a
} by {
- ; Peephole 246.e combined set/clr/clr
+ ; Peephole 246.e combined set/clr/clr
mov dptr,#%1
movx a,@dptr
orl a,#%2
orl a,#%4
movx @dptr,a
} by {
- ; Peephole 246.f combined set/clr/set
+ ; Peephole 246.f combined set/clr/set
mov dptr,#%1
movx a,@dptr
orl a,#%2
anl a,#%4
movx @dptr,a
} by {
- ; Peephole 246.g combined clr/set/clr
+ ; Peephole 246.g combined clr/set/clr
mov dptr,#%1
movx a,@dptr
anl a,#%2
orl a,#%4
movx @dptr,a
} by {
- ; Peephole 246.h combined clr/set/set
+ ; Peephole 246.h combined clr/set/set
mov dptr,#%1
movx a,@dptr
anl a,#%2
anl a,#%3
mov @r%5,a
} by {
- ; Peephole 247.a combined clr/clr
+ ; Peephole 247.a combined clr/clr
mov r%5,#%1
mov a,@r%5
anl a,#%2&%3
orl a,#%3
mov @r%5,a
} by {
- ; Peephole 247.b combined set/set
+ ; Peephole 247.b combined set/set
mov r%5,#%1
mov a,@r%5
orl a,#%2|%3
anl a,#%3
mov @r%5,a
} by {
- ; Peephole 247.c combined set/clr
+ ; Peephole 247.c combined set/clr
mov r%5,#%1
mov a,@r%5
orl a,#%2
orl a,#%3
mov @r%5,a
} by {
- ; Peephole 247.d combined clr/set
+ ; Peephole 247.d combined clr/set
mov r%5,#%1
mov a,@r%5
anl a,#%2
anl a,#%4
mov @r%5,a
} by {
- ; Peephole 247.e combined set/clr/clr
+ ; Peephole 247.e combined set/clr/clr
mov r%5,#%1
mov a,@r%5
orl a,#%2
orl a,#%4
mov @r%5,a
} by {
- ; Peephole 247.f combined set/clr/set
+ ; Peephole 247.f combined set/clr/set
mov r%5,#%1
mov a,@r%5
orl a,#%2
anl a,#%4
mov @r%5,a
} by {
- ; Peephole 247.g combined clr/set/clr
+ ; Peephole 247.g combined clr/set/clr
mov r%5,#%1
mov a,@r%5
anl a,#%2
orl a,#%4
mov @r%5,a
} by {
- ; Peephole 247.h combined clr/set/set
+ ; Peephole 247.h combined clr/set/set
mov r%5,#%1
mov a,@r%5
anl a,#%2
// Peepholes 248.x have to be compatible with the keyword volatile.
// They optimize typical accesses to memory mapped I/O devices:
-// volatile xdata char t; t|=0x01;
+// volatile xdata char t; t|=0x01;
replace {
mov dptr,%1
movx a,@dptr
movx @dptr,a
}
-// volatile xdata char t; t&=0x01;
+// volatile xdata char t; t&=0x01;
replace {
mov dptr,%1
movx a,@dptr
movx @dptr,a
}
-// volatile xdata char t; t^=0x01;
+// volatile xdata char t; t^=0x01;
replace {
mov dptr,%1
movx a,@dptr
jnz %1
%1:
} by {
- ; Peephole 249a jump optimization
+ ; Peephole 249.a jump optimization
} if labelRefCount %1 1
replace {
jz %1
%1:
} by {
- ; Peephole 249b jump optimization
+ ; Peephole 249.b jump optimization
} if labelRefCount %1 1
ret
}
+
// applies to f.e. funptrs.c
// saves one byte if %1 is a register or @register
replace {
mov dptr,%5
jmp @a+dptr
}
+
+// applies to f.e. jump tables and scott-bool1.c.
+// similar peepholes can be constructed for other instructions
+// after which a flag or a register is known (like: djnz, cjne, jnc)
+replace {
+ jc %1
+%2:
+ clr c
+} by {
+ ; Peephole 256.a removed redundant clr c
+ jc %1
+%2:
+} if labelRefCount %2 0
+
+// applies to f.e. logf.c
+replace {
+ jnz %1
+%2:
+ clr a
+} by {
+ ; Peephole 256.b removed redundant clr a
+ jnz %1
+%2:
+} if labelRefCount %2 0
+
+
+// unsigned char i=8; do{ } while(--i != 0);
+// this currently only applies if i is kept in a register
+replace {
+ dec %1
+ cjne %1,#0x00,%2
+} by {
+ ; Peephole 257 optimized decrement with compare
+ djnz %1,%2
+} if notVolatile %1
+
+
+// in_byte<<=1; if(in_bit) in_byte|=1;
+// helps f.e. reading data on a 3-wire (SPI) bus
+replace {
+ mov a,%1
+ add a,%1
+ mov %1,a
+ jnb %2,%3
+%4:
+ orl %1,#0x01
+%3:
+} by {
+ ; Peephole 258.a optimized bitbanging
+ mov a,%1
+ mov c,%2
+ addc a,%1
+ mov %1,a
+%4:
+%3:
+} if notVolatile %1
+
+// in_byte<<=1; if(in_bit) in_byte|=1;
+replace {
+ mov a,r%1
+ add a,r%1
+ mov r%1,a
+ jnb %2,%3
+%4:
+ orl ar%1,#0x01
+%3:
+} by {
+ ; Peephole 258.b optimized bitbanging
+ mov a,r%1
+ mov c,%2
+ addc a,r%1
+ mov r%1,a
+%4:
+%3:
+}
+
+// in_byte>>=1; if(in_bit) in_byte|=0x80;
+replace {
+ mov a,%1
+ clr c
+ rrc a
+ mov %1,a
+ jnb %2,%3
+%4:
+ orl %1,#0x80
+%3:
+} by {
+ ; Peephole 258.c optimized bitbanging
+ mov a,%1
+ mov c,%2
+ rrc a
+ mov %1,a
+%4:
+%3:
+} if notVolatile %1
+
+// in_byte>>=1; if(in_bit) in_byte|=0x80;
+replace {
+ mov a,r%1
+ clr c
+ rrc a
+ mov r%1,a
+ jnb %2,%3
+%4:
+ orl ar%1,#0x80
+%3:
+} by {
+ ; Peephole 258.d optimized bitbanging
+ mov a,r%1
+ mov c,%2
+ rrc a
+ mov r%1,a
+%4:
+%3:
+}
+
+// out_bit=out_byte&0x80; out_byte<<=1;
+// helps f.e. writing data on a 3-wire (SPI) bus
+replace {
+ mov a,%1
+ mov c,acc.7
+ mov %2,c
+ mov a,%1
+ add a,%1
+ mov %1,a
+} by {
+ ; Peephole 258.e optimized bitbanging
+ mov a,%1
+ add a,%1
+ mov %2,c
+ mov %1,a
+} if notVolatile %1
+
+// out_bit=out_byte&0x01; out_byte>>=1;
+replace {
+ mov a,%1
+ mov c,acc.0
+ mov %2,c
+ mov a,%1
+ clr c
+ rrc a
+ mov %1,a
+} by {
+ ; Peephole 258.f optimized bitbanging
+ mov a,%1
+ clr c
+ rrc a
+ mov %2,c
+ mov %1,a
+} if notVolatile %1
+
projects / fw / sdcc / blobdiff