* as/mcs51/asdata.c: changed ctype['['] to BINOP

[fw/sdcc] / src / mcs51 / main.c

diff --git a/src/mcs51/main.c b/src/mcs51/main.c
index 0ea349c4f2f2c99db9c11426a6546a73c84bad56..a8854a78b672ebabc630183756e6595e327b79b5 100644 (file)
--- a/src/mcs51/main.c
+++ b/src/mcs51/main.c
@@ -19,6 +19,7 @@ static char _defaultRules[] =
 static char *_mcs51_keywords[] =
 {
   "at",
+  "banked",
   "bit",
   "code",
   "critical",
@@ -30,6 +31,8 @@ static char *_mcs51_keywords[] =
   "pdata",
   "reentrant",
   "sfr",
+  "sfr16",
+  "sfr32",
   "sbit",
   "using",
   "xdata",
@@ -50,6 +53,7 @@ static char *_mcs51_keywords[] =
 void mcs51_assignRegisters (ebbIndex *);
 
 static int regParmFlg = 0;      /* determine if we can register a parameter */
+static int regBitParmFlg = 0;   /* determine if we can register a bit parameter */
 
 static void
 _mcs51_init (void)
@@ -61,13 +65,20 @@ static void
 _mcs51_reset_regparm (void)
 {
   regParmFlg = 0;
+  regBitParmFlg = 0;
 }
 
 static int
 _mcs51_regparm (sym_link * l)
 {
-    if (IS_SPEC(l) && (SPEC_NOUN(l) == V_BIT))
+    if (IS_SPEC(l) && (SPEC_NOUN(l) == V_BIT)) {
+        /* bit parameters go to b0 thru b7 */
+        if (options.stackAuto && (regBitParmFlg < 8)) {
+            regBitParmFlg++;
+            return 12 + regBitParmFlg;
+        }
         return 0;
+    }
     if (options.parms_in_bank1 == 0) {
         /* simple can pass only the first parameter in a register */
         if (regParmFlg)
@@ -179,13 +190,16 @@ _mcs51_genIVT (FILE * of, symbol ** interrupts, int maxInterrupts)
 static void
 _mcs51_genExtraAreas(FILE *of, bool hasMain)
 {
-  tfprintf (of, "\t!area\n", port->mem.code_name);
+  tfprintf (of, "\t!area\n", HOME_NAME);
   tfprintf (of, "\t!area\n", "GSINIT0 (CODE)");
   tfprintf (of, "\t!area\n", "GSINIT1 (CODE)");
   tfprintf (of, "\t!area\n", "GSINIT2 (CODE)");
   tfprintf (of, "\t!area\n", "GSINIT3 (CODE)");
   tfprintf (of, "\t!area\n", "GSINIT4 (CODE)");
   tfprintf (of, "\t!area\n", "GSINIT5 (CODE)");
+  tfprintf (of, "\t!area\n", STATIC_NAME);
+  tfprintf (of, "\t!area\n", port->mem.post_static_name);
+  tfprintf (of, "\t!area\n", CODE_NAME);
 }
 
 static void
@@ -706,31 +720,37 @@ PORT mcs51_port =
     1, 2, 2, 4, 1, 2, 3, 1, 4, 4
   },
   {
-    "XSTK    (PAG,XDATA)",
-    "STACK   (DATA)",
-    "CSEG    (CODE)",
-    "DSEG    (DATA)",
-    "ISEG    (DATA)",
-    "PSEG    (PAG,XDATA)",
-    "XSEG    (XDATA)",
-    "BSEG    (BIT)",
-    "RSEG    (DATA)",
-    "GSINIT  (CODE)",
-    "OSEG    (OVR,DATA)",
-    "GSFINAL (CODE)",
-    "HOME    (CODE)",
-    "XISEG   (XDATA)", // initialized xdata
-    "XINIT   (CODE)", // a code copy of xiseg
+    "XSTK    (PAG,XDATA)",      // xstack_name
+    "STACK   (DATA)",          // istack_name
+    "CSEG    (CODE)",          // code_name
+    "DSEG    (DATA)",          // data_name
+    "ISEG    (DATA)",          // idata_name
+    "PSEG    (PAG,XDATA)",     // pdata_name
+    "XSEG    (XDATA)",         // xdata_name
+    "BSEG    (BIT)",           // bit_name
+    "RSEG    (DATA)",          // reg_name
+    "GSINIT  (CODE)",          // static_name
+    "OSEG    (OVR,DATA)",      // overlay_name
+    "GSFINAL (CODE)",          // post_static_name
+    "HOME    (CODE)",          // home_name
+    "XISEG   (XDATA)",         // xidata_name - initialized xdata   initialized xdata
+    "XINIT   (CODE)",          // xinit_name - a code copy of xiseg
+    "CONST   (CODE)",          // const_name - const data (code or not)
     NULL,
     NULL,
     1
   },
   { _mcs51_genExtraAreas, NULL },
   {
-    +1, 0, 4, 1, 1, 0
+    +1,                /* direction (+1 = stack grows up) */
+    0,         /* bank_overhead (switch between register banks) */
+    4,         /* isr_overhead */
+    1,         /* call_overhead (2 for return address - 1 for pre-incrementing push */
+    1,         /* reent_overhead */
+    0          /* banked_overhead (switch between code banks) */
   },
-    /* mcs51 has an 8 bit mul */
   {
+    /* mcs51 has an 8 bit mul */
     1, -1
   },
   {