#ifndef SWD_H
#define SWD_H
+#include <target/arm_adi_v5.h>
+
/* Bits in SWD command packets, written from host to target
* first bit on the wire is START
*/
#define SWD_CMD_A32 (3 << 3) /* bits A[3:2] of register addr */
#define SWD_CMD_PARITY (1 << 5) /* parity of APnDP|RnW|A32 */
#define SWD_CMD_STOP (0 << 6) /* always clear for synch SWD */
-#define SWD_CMD_PARK (0 << 7) /* not driven by host (pull high) */
+#define SWD_CMD_PARK (1 << 7) /* driven high by host */
/* followed by TRN, 3-bits of ACK, TRN */
-/* pbit16 holds precomputed parity bits for each nibble */
-#define pbit(parity, nibble) ((parity) << (nibble))
-
-static const uint16_t pbit16 =
- pbit(0, 0) | pbit(1, 1) | pbit(1, 2) | pbit(0, 3)
- | pbit(1, 4) | pbit(0, 5) | pbit(0, 6) | pbit(1, 7)
- | pbit(1, 8) | pbit(0, 9) | pbit(0, 0xa) | pbit(1, 0xb)
- | pbit(0, 0xc) | pbit(1, 0xd) | pbit(1, 0xe) | pbit(0, 0xf);
-
-#define nibble_parity(nibble) (pbit16 & pbit(1, (nibble)))
-
/**
* Construct a "cmd" byte, in lSB bit order, which swd_driver.read_reg()
* and swd_driver.write_reg() methods will use directly.
| ((regnum & 0xc) << 1);
/* 8 cmd bits 4:1 may be set */
- if (nibble_parity(cmd >> 1))
+ if (parity_u32(cmd))
cmd |= SWD_CMD_PARITY;
/* driver handles START, STOP, and TRN */
/* SWD_ACK_* bits are defined in <target/arm_adi_v5.h> */
-/*
- * FOR NOW ... SWD driver ops are synchronous and return ACK
- * status ... no queuing.
+/**
+ * Line reset.
+ *
+ * Line reset is at least 50 SWCLK cycles with SWDIO driven high, followed
+ * by at least one idle (low) cycle.
+ */
+static const uint8_t swd_seq_line_reset[] = {
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x03
+};
+static const unsigned swd_seq_line_reset_len = 51;
+
+/**
+ * JTAG-to-SWD sequence.
+ *
+ * The JTAG-to-SWD sequence is at least 50 TCK/SWCLK cycles with TMS/SWDIO
+ * high, putting either interface logic into reset state, followed by a
+ * specific 16-bit sequence and finally a line reset in case the SWJ-DP was
+ * already in SWD mode.
+ */
+static const uint8_t swd_seq_jtag_to_swd[] = {
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7b, 0x9e,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x0f,
+};
+static const unsigned swd_seq_jtag_to_swd_len = 118;
+
+/**
+ * SWD-to-JTAG sequence.
*
- * Individual ops are request/response, and fast-fail permits much
- * better fault handling. Upper layers may queue if desired.
+ * The SWD-to-JTAG sequence is at least 50 TCK/SWCLK cycles with TMS/SWDIO
+ * high, putting either interface logic into reset state, followed by a
+ * specific 16-bit sequence and finally at least 5 TCK cycles to put the
+ * JTAG TAP in TLR.
*/
+static const uint8_t swd_seq_swd_to_jtag[] = {
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf3, 0x9c, 0xff
+};
+static const unsigned swd_seq_swd_to_jtag_len = 71;
+
+/**
+ * SWD-to-dormant sequence.
+ *
+ * This is at least 50 SWCLK cycles with SWDIO high to put the interface
+ * in reset state, followed by a specific 16-bit sequence.
+ */
+static const uint8_t swd_seq_swd_to_dormant[] = {
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf3, 0x8e, 0x03
+};
+static const unsigned swd_seq_swd_to_dormant_len = 66;
+
+/**
+ * Dormant-to-SWD sequence.
+ *
+ * This is at least 8 TCK/SWCLK cycles with TMS/SWDIO high to abort any ongoing
+ * selection alert sequence, followed by a specific 128-bit selection alert
+ * sequence, followed by 4 TCK/SWCLK cycles with TMS/SWDIO low, followed by
+ * a specific protocol-dependent activation code. For SWD the activation code
+ * is an 8-bit sequence. The sequence ends with a line reset.
+ */
+static const uint8_t swd_seq_dormant_to_swd[] = {
+ 0xff,
+ 0x92, 0xf3, 0x09, 0x62, 0x95, 0x2d, 0x85, 0x86,
+ 0xe9, 0xaf, 0xdd, 0xe3, 0xa2, 0x0e, 0xbc, 0x19,
+ 0x10, 0xfa, 0xff, 0xff, 0xff, 0xff, 0xff, 0x3f
+};
+static const unsigned swd_seq_dormant_to_swd_len = 199;
+
+enum swd_special_seq {
+ LINE_RESET,
+ JTAG_TO_SWD,
+ SWD_TO_JTAG,
+ SWD_TO_DORMANT,
+ DORMANT_TO_SWD,
+};
struct swd_driver {
/**
- * Initialize the debug link so it can perform
- * synchronous SWD operations.
- * @param trn value from WCR: how many clocks
- * to not drive the SWDIO line at certain points in
- * the SWD protocol (at least 1 clock).
+ * Initialize the debug link so it can perform SWD operations.
*
* As an example, this would switch a dual-mode debug adapter
* into SWD mode and out of JTAG mode.
- *
- * @return ERROR_OK on success, else a negative fault code.
+ *
+ * @return ERROR_OK on success, else a negative fault code.
*/
- int (*init)(uint8_t trn);
-
-
- /**
- * Synchronous read of an AP or DP register.
- *
- * @param cmd with APnDP/RnW/addr/parity bits
- * @param where to store value to read from register
- *
- * @return SWD_ACK_* code for the transaction
- * or (negative) fault code
- */
- int (*read_reg)(uint8_t cmd, uint32_t *value);
-
- /**
- * Synchronous write of an AP or DP register.
- *
- * @param cmd with APnDP/RnW/addr/parity bits
- * @param value to be written to the register
- *
- * @return SWD_ACK_* code for the transaction
- * or (negative) fault code
- */
- int (*write_reg)(uint8_t cmd, uint32_t value);
+ int (*init)(void);
+
+ /**
+ * Set the SWCLK frequency of the SWD link.
+ *
+ * The driver should round the desired value, downwards if possible, to
+ * the nearest supported frequency. A negative value should be ignored
+ * and can be used to query the current setting. If the driver does not
+ * support a variable frequency a fixed, nominal, value should be
+ * returned.
+ *
+ * If the frequency is increased, it must not apply before the currently
+ * queued transactions are executed. If the frequency is lowered, it may
+ * apply immediately.
+ *
+ * @param dap The DAP controlled by the SWD link.
+ * @param hz The desired frequency in Hz.
+ * @return The actual resulting frequency after rounding.
+ */
+ int_least32_t (*frequency)(struct adiv5_dap *dap, int_least32_t hz);
+
+ /**
+ * Queue a special SWDIO sequence.
+ *
+ * @param dap The DAP controlled by the SWD link.
+ * @param seq The special sequence to generate.
+ * @return ERROR_OK if the sequence was queued, negative error if the
+ * sequence is unsupported.
+ */
+ int (*switch_seq)(struct adiv5_dap *dap, enum swd_special_seq seq);
+
+ /**
+ * Queued read of an AP or DP register.
+ *
+ * @param dap The DAP controlled by the SWD link.
+ * @param Command byte with APnDP/RnW/addr/parity bits
+ * @param Where to store value to read from register
+ */
+ void (*read_reg)(struct adiv5_dap *dap, uint8_t cmd, uint32_t *value);
+
+ /**
+ * Queued write of an AP or DP register.
+ *
+ * @param dap The DAP controlled by the SWD link.
+ * @param Command byte with APnDP/RnW/addr/parity bits
+ * @param Value to be written to the register
+ */
+ void (*write_reg)(struct adiv5_dap *dap, uint8_t cmd, uint32_t value);
+
+ /**
+ * Execute any queued transactions and collect the result.
+ *
+ * @param dap The DAP controlled by the SWD link.
+ * @return ERROR_OK on success, Ack response code on WAIT/FAULT
+ * or negative error code on other kinds of failure.
+ */
+ int (*run)(struct adiv5_dap *dap);
/**
* Configures data collection from the Single-wire
* is normally connected to a microcontroller's UART TX,
* but which may instead be connected to SWO for use in
* collecting ITM (and possibly ETM) trace data.
- *
- * @return ERROR_OK on success, else a negative fault code.
+ *
+ * @return ERROR_OK on success, else a negative fault code.
*/
- int *(*trace)(bool swo);
+ int *(*trace)(struct adiv5_dap *dap, bool swo);
};
int swd_init_reset(struct command_context *cmd_ctx);
void swd_add_reset(int req_srst);
bool transport_is_swd(void);
-bool transport_is_cmsis_dap(void);
#endif /* SWD_H */
projects / fw / openocd / blobdiff