swd: Fix park bit polarity according to ADIv5.1 Supplement

[fw/openocd] / src / jtag / swd.h

diff --git a/src/jtag/swd.h b/src/jtag/swd.h
index fee7f912a3e37b8aed858541817e89a294348bb8..2e676b50f4d5b2a69f24358bc01f1bb2878905f1 100644 (file)
--- a/src/jtag/swd.h
+++ b/src/jtag/swd.h
@@ -20,6 +20,8 @@
 #ifndef SWD_H
 #define SWD_H
 
+#include <target/arm_adi_v5.h>
+
 /* Bits in SWD command packets, written from host to target
  * first bit on the wire is START
  */
@@ -29,20 +31,9 @@
 #define SWD_CMD_A32    (3 << 3)                /* bits A[3:2] of register addr */
 #define SWD_CMD_PARITY (1 << 5)        /* parity of APnDP|RnW|A32 */
 #define SWD_CMD_STOP   (0 << 6)        /* always clear for synch SWD */
-#define SWD_CMD_PARK   (0 << 7)        /* not driven by host (pull high) */
+#define SWD_CMD_PARK   (1 << 7)        /* driven high by host */
 /* followed by TRN, 3-bits of ACK, TRN */
 
-/* pbit16 holds precomputed parity bits for each nibble */
-#define pbit(parity, nibble) ((parity) << (nibble))
-
-static const uint16_t pbit16 =
-       pbit(0, 0) | pbit(1, 1) | pbit(1, 2) | pbit(0, 3)
-       | pbit(1, 4) | pbit(0, 5) | pbit(0, 6) | pbit(1, 7)
-       | pbit(1, 8) | pbit(0, 9) | pbit(0, 0xa) | pbit(1, 0xb)
-       | pbit(0, 0xc) | pbit(1, 0xd) | pbit(1, 0xe) | pbit(0, 0xf);
-
-#define nibble_parity(nibble) (pbit16 & pbit(1, (nibble)))
-
 /**
  * Construct a "cmd" byte, in lSB bit order, which swd_driver.read_reg()
  * and swd_driver.write_reg() methods will use directly.
@@ -54,7 +45,7 @@ static inline uint8_t swd_cmd(bool is_read, bool is_ap, uint8_t regnum)
                | ((regnum & 0xc) << 1);
 
        /* 8 cmd bits 4:1 may be set */
-       if (nibble_parity(cmd >> 1))
+       if (parity_u32(cmd))
                cmd |= SWD_CMD_PARITY;
 
        /* driver handles START, STOP, and TRN */
@@ -64,63 +55,47 @@ static inline uint8_t swd_cmd(bool is_read, bool is_ap, uint8_t regnum)
 
 /* SWD_ACK_* bits are defined in <target/arm_adi_v5.h> */
 
-/*
- * FOR NOW  ... SWD driver ops are synchronous and return ACK
- * status ... no quueueing.
- *
- * Individual ops are request/response, and fast-fail permits much
- * better fault handling.  Upper layers may queue if desired.
- */
-
 struct swd_driver {
        /**
-        * Initialize the debug link so it can perform
-        * synchronous SWD operations.
+        * Initialize the debug link so it can perform SWD operations.
         * @param trn value from WCR: how many clocks
         * to not drive the SWDIO line at certain points in
         * the SWD protocol (at least 1 clock).
         *
         * As an example, this would switch a dual-mode debug adapter
         * into SWD mode and out of JTAG mode.
-         *
-         * @return ERROR_OK on success, else a negative fault code.
+        *
+        * @return ERROR_OK on success, else a negative fault code.
         */
        int (*init)(uint8_t trn);
 
 
-        /**
-         * Synchronous read of an AP or DP register.
-         *
-         * @param cmd with APnDP/RnW/addr/parity bits
-         * @param where to store value to read from register
-         *
-         * @return SWD_ACK_* code for the transaction
-         *             or (negative) fault code
-         */
-        int (*read_reg)(uint8_t cmd, uint32_t *value);
-
-        /**
-         * Synchronous write of an AP or DP register.
-         *
-         * @param cmd with APnDP/RnW/addr/parity bits
-         * @param value to be written to the register
-         *
-         * @return SWD_ACK_* code for the transaction
-         *             or (negative) fault code
-         */
-        int (*write_reg)(uint8_t cmd, uint32_t value);
-
-        /**
-         * Synchronous block read of an AP or DP register.
-         *
-         * @param cmd with APnDP/RnW/addr/parity bits
-         * @param number of reads from register to be executed
-         * @param buffer to store data read from register
-         *
-         * @return SWD_ACK_* code for the transaction
-         *             or (negative) fault code
-         */
-        int (*read_block)(uint8_t cmd, uint32_t blocksize, uint8_t *buffer);
+       /**
+        * Queued read of an AP or DP register.
+        *
+        * @param dap The DAP controlled by the SWD link.
+        * @param Command byte with APnDP/RnW/addr/parity bits
+        * @param Where to store value to read from register
+        */
+       void (*read_reg)(struct adiv5_dap *dap, uint8_t cmd, uint32_t *value);
+
+       /**
+        * Queued write of an AP or DP register.
+        *
+        * @param dap The DAP controlled by the SWD link.
+        * @param Command byte with APnDP/RnW/addr/parity bits
+        * @param Value to be written to the register
+        */
+       void (*write_reg)(struct adiv5_dap *dap, uint8_t cmd, uint32_t value);
+
+       /**
+        * Execute any queued transactions and collect the result.
+        *
+        * @param dap The DAP controlled by the SWD link.
+        * @return ERROR_OK on success, Ack response code on WAIT/FAULT
+        * or negative error code on other kinds of failure.
+        */
+       int (*run)(struct adiv5_dap *dap);
 
        /**
         * Configures data collection from the Single-wire
@@ -131,10 +106,10 @@ struct swd_driver {
         * is normally connected to a microcontroller's UART TX,
         * but which may instead be connected to SWO for use in
         * collecting ITM (and possibly ETM) trace data.
-         *
-         * @return ERROR_OK on success, else a negative fault code.
+        *
+        * @return ERROR_OK on success, else a negative fault code.
         */
-       int *(*trace)(bool swo);
+       int *(*trace)(struct adiv5_dap *dap, bool swo);
 };
 
 int swd_init_reset(struct command_context *cmd_ctx);