#include "gdb-remote.h"
#include "stlink-hw.h"
+#define FLASH_BASE 0x08000000
+#define FLASH_PAGE (sl->flash_pgsz)
+#define FLASH_PAGE_MASK (~((1 << 10) - 1))
+#define FLASH_SIZE (FLASH_PAGE * 128)
+
static const char hex[] = "0123456789abcdef";
-// configured for STM32F100RB
-static const char* const c_memory_map =
- "<?xml version=\"1.0\"?>"
- "<!DOCTYPE memory-map PUBLIC \"+//IDN gnu.org//DTD GDB Memory Map V1.0//EN\""
- " \"http://sourceware.org/gdb/gdb-memory-map.dtd\">"
- "<memory-map>"
- " <memory type=\"rom\" start=\"0x00000000\" length=\"0x100000\"/>" // code
- " <memory type=\"ram\" start=\"0x20000000\" length=\"0x100000\"/>" // sram
- " <memory type=\"flash\" start=\"0x08000000\" length=\"0x20000\">" // flash 128k
- " <property name=\"blocksize\">0x400</property>" // 1k pages
- " </memory>"
- "</memory-map>";
+static const char* current_memory_map = NULL;
+
+struct chip_params {
+ uint32_t chip_id;
+ char* description;
+ uint32_t max_flash_size, flash_pagesize;
+ uint32_t sram_size;
+ uint32_t bootrom_base, bootrom_size;
+} const devices[] = {
+ { 0x412, "Low-density device",
+ 0x8000, 0x400, 0x2800, 0x1ffff000, 0x800 },
+ { 0x410, "Medium-density device",
+ 0x20000, 0x400, 0x5000, 0x1ffff000, 0x800 },
+ { 0x414, "High-density device",
+ 0x80000, 0x800, 0x10000, 0x1ffff000, 0x800 },
+ { 0x418, "Connectivity line device",
+ 0x40000, 0x800, 0x10000, 0x1fffb000, 0x4800 },
+ { 0x420, "Medium-density value line device",
+ 0x20000, 0x400, 0x2000, 0x1ffff000, 0x800 },
+ { 0x428, "High-density value line device",
+ 0x80000, 0x800, 0x8000, 0x1ffff000, 0x800 },
+ { 0x430, "XL-density device",
+ 0x100000, 0x800, 0x18000, 0x1fffe000, 0x1800 },
+ { 0 }
+};
int serve(struct stlink* sl, int port);
+char* make_memory_map(const struct chip_params *params, uint32_t flash_size);
int main(int argc, char** argv) {
- if(argc != 3) {
- fprintf(stderr, "Usage: %s <port> /dev/sgX\n", argv[0]);
- return 1;
- }
- struct stlink *sl = stlink_quirk_open(argv[2], 0);
- if (sl == NULL)
- return 1;
+ struct stlink *sl = NULL;
+
+ switch(argc) {
+
+ default: {
+ fprintf(stderr, "Usage: %s <port> [/dev/sgX] \n", argv[0]);
+ return 1;
+ }
+
+ case 3 : {
+ sl = stlink_quirk_open(argv[2], 0);
+ if(sl == NULL) return 1;
+ break;
+ }
+
+ case 2 : { // Search ST-LINK (from /dev/sg0 to /dev/sg99)
+ const int DevNumMax = 99;
+ int ExistDevCount = 0;
+
+ for(int DevNum = 0; DevNum <= DevNumMax; DevNum++)
+ {
+ if(DevNum < 10) {
+ char DevName[] = "/dev/sgX";
+ const int X_index = 7;
+ DevName[X_index] = DevNum + '0';
+ if ( !access(DevName, F_OK) ) {
+ sl = stlink_quirk_open(DevName, 0);
+ ExistDevCount++;
+ }
+ }
+ else if(DevNum < 100) {
+ char DevName[] = "/dev/sgXY";
+ const int X_index = 7;
+ const int Y_index = 8;
+ DevName[X_index] = DevNum/10 + '0';
+ DevName[Y_index] = DevNum%10 + '0';
+ if ( !access(DevName, F_OK) ) {
+ sl = stlink_quirk_open(DevName, 0);
+ ExistDevCount++;
+ }
+ }
+ if(sl != NULL) break;
+ }
+
+ if(sl == NULL) {
+ fprintf(stdout, "\nNumber of /dev/sgX devices found: %i \n",
+ ExistDevCount);
+ fprintf(stderr, "ST-LINK not found\n");
+ return 1;
+ }
+ break;
+ }
+ }
if(stlink_current_mode(sl) != STLINK_DEV_DEBUG_MODE)
stlink_enter_swd_mode(sl);
- stlink_core_id(sl);
- printf("Debugging ARM core %08x.\n", sl->core_id);
+ uint32_t chip_id;
+
+ stlink_read_mem32(sl, 0xE0042000, 4);
+ chip_id = sl->q_buf[0] | (sl->q_buf[1] << 8) | (sl->q_buf[2] << 16) |
+ (sl->q_buf[3] << 24);
+
+ printf("Chip ID is %08x.\n", chip_id);
+
+ const struct chip_params* params = NULL;
+
+ for(int i = 0; i < sizeof(devices) / sizeof(devices[0]); i++) {
+ if(devices[i].chip_id == (chip_id & 0xFFF)) {
+ params = &devices[i];
+ break;
+ }
+ }
+
+ if(params == NULL) {
+ fprintf(stderr, "Cannot recognize the connected device!\n");
+ return 0;
+ }
+
+ printf("Device connected: %s\n", params->description);
+ printf("Device parameters: SRAM: 0x%x bytes, Flash: up to 0x%x bytes in pages of 0x%x bytes\n",
+ params->sram_size, params->max_flash_size, params->flash_pagesize);
+
+ FLASH_PAGE = params->flash_pagesize;
+
+ uint32_t flash_size;
+
+ stlink_read_mem32(sl, 0x1FFFF7E0, 4);
+ flash_size = sl->q_buf[0] | (sl->q_buf[1] << 8);
+
+ printf("Flash size is %d KiB.\n", flash_size);
+ // memory map is in 1k blocks.
+ current_memory_map = make_memory_map(params, flash_size * 0x400);
int port = atoi(argv[1]);
return 0;
}
+static const char* const memory_map_template =
+ "<?xml version=\"1.0\"?>"
+ "<!DOCTYPE memory-map PUBLIC \"+//IDN gnu.org//DTD GDB Memory Map V1.0//EN\""
+ " \"http://sourceware.org/gdb/gdb-memory-map.dtd\">"
+ "<memory-map>"
+ " <memory type=\"rom\" start=\"0x00000000\" length=\"0x%x\"/>" // code = sram, bootrom or flash; flash is bigger
+ " <memory type=\"ram\" start=\"0x20000000\" length=\"0x%x\"/>" // sram 8k
+ " <memory type=\"flash\" start=\"0x08000000\" length=\"0x%x\">"
+ " <property name=\"blocksize\">0x%x</property>"
+ " </memory>"
+ " <memory type=\"ram\" start=\"0x40000000\" length=\"0x1fffffff\"/>" // peripheral regs
+ " <memory type=\"ram\" start=\"0xe0000000\" length=\"0x1fffffff\"/>" // cortex regs
+ " <memory type=\"rom\" start=\"0x%08x\" length=\"0x%x\"/>" // bootrom
+ " <memory type=\"rom\" start=\"0x1ffff800\" length=\"0x8\"/>" // option byte area
+ "</memory-map>";
+
+char* make_memory_map(const struct chip_params *params, uint32_t flash_size) {
+ /* This will be freed in serve() */
+ char* map = malloc(4096);
+ map[0] = '\0';
+
+ snprintf(map, 4096, memory_map_template,
+ flash_size,
+ params->sram_size,
+ flash_size, params->flash_pagesize,
+ params->bootrom_base, params->bootrom_size);
+
+ return map;
+}
+
+
+/*
+ * DWT_COMP0 0xE0001020
+ * DWT_MASK0 0xE0001024
+ * DWT_FUNCTION0 0xE0001028
+ * DWT_COMP1 0xE0001030
+ * DWT_MASK1 0xE0001034
+ * DWT_FUNCTION1 0xE0001038
+ * DWT_COMP2 0xE0001040
+ * DWT_MASK2 0xE0001044
+ * DWT_FUNCTION2 0xE0001048
+ * DWT_COMP3 0xE0001050
+ * DWT_MASK3 0xE0001054
+ * DWT_FUNCTION3 0xE0001058
+ */
+
+#define DATA_WATCH_NUM 4
+
+enum watchfun { WATCHDISABLED = 0, WATCHREAD = 5, WATCHWRITE = 6, WATCHACCESS = 7 };
+
+struct code_hw_watchpoint {
+ stm32_addr_t addr;
+ uint8_t mask;
+ enum watchfun fun;
+};
+
+struct code_hw_watchpoint data_watches[DATA_WATCH_NUM];
+
+static void init_data_watchpoints(struct stlink *sl) {
+ int i;
+
+ #ifdef DEBUG
+ printf("init watchpoints\n");
+ #endif
+
+ // set trcena in debug command to turn on dwt unit
+ stlink_read_mem32(sl, 0xE000EDFC, 4);
+ sl->q_buf[3] |= 1;
+ stlink_write_mem32(sl, 0xE000EDFC, 4);
+
+ // make sure all watchpoints are cleared
+ memset(sl->q_buf, 0, 4);
+ for(int i = 0; i < DATA_WATCH_NUM; i++) {
+ data_watches[i].fun = WATCHDISABLED;
+ stlink_write_mem32(sl, 0xe0001028 + i * 16, 4);
+ }
+}
+
+static int add_data_watchpoint(struct stlink* sl, enum watchfun wf, stm32_addr_t addr, unsigned int len)
+{
+ int i = 0;
+ uint32_t mask, temp;
+
+ // computer mask
+ // find a free watchpoint
+ // configure
+
+ mask = -1;
+ i = len;
+ while(i) {
+ i >>= 1;
+ mask++;
+ }
+
+ if((mask != -1) && (mask < 16)) {
+ for(i = 0; i < DATA_WATCH_NUM; i++) {
+ // is this an empty slot ?
+ if(data_watches[i].fun == WATCHDISABLED) {
+ #ifdef DEBUG
+ printf("insert watchpoint %d addr %x wf %u mask %u len %d\n", i, addr, wf, mask, len);
+ #endif
+
+ data_watches[i].fun = wf;
+ data_watches[i].addr = addr;
+ data_watches[i].mask = mask;
+
+ // insert comparator address
+ sl->q_buf[0] = (addr & 0xff);
+ sl->q_buf[1] = ((addr >> 8) & 0xff);
+ sl->q_buf[2] = ((addr >> 16) & 0xff);
+ sl->q_buf[3] = ((addr >> 24) & 0xff);
+
+ stlink_write_mem32(sl, 0xE0001020 + i * 16, 4);
+
+ // insert mask
+ memset(sl->q_buf, 0, 4);
+ sl->q_buf[0] = mask;
+ stlink_write_mem32(sl, 0xE0001024 + i * 16, 4);
+
+ // insert function
+ memset(sl->q_buf, 0, 4);
+ sl->q_buf[0] = wf;
+ stlink_write_mem32(sl, 0xE0001028 + i * 16, 4);
+
+ // just to make sure the matched bit is clear !
+ stlink_read_mem32(sl, 0xE0001028 + i * 16, 4);
+ return 0;
+ }
+ }
+ }
+
+ #ifdef DEBUG
+ printf("failure: add watchpoints addr %x wf %u len %u\n", addr, wf, len);
+ #endif
+ return -1;
+}
+
+static int delete_data_watchpoint(struct stlink* sl, stm32_addr_t addr)
+{
+ int i;
+
+ for(i = 0 ; i < DATA_WATCH_NUM; i++) {
+ if((data_watches[i].addr == addr) && (data_watches[i].fun != WATCHDISABLED)) {
+ #ifdef DEBUG
+ printf("delete watchpoint %d addr %x\n", i, addr);
+ #endif
+
+ memset(sl->q_buf, 0, 4);
+ data_watches[i].fun = WATCHDISABLED;
+ stlink_write_mem32(sl, 0xe0001028 + i * 16, 4);
+
+ return 0;
+ }
+ }
+
+ #ifdef DEBUG
+ printf("failure: delete watchpoint addr %x\n", addr);
+ #endif
+
+ return -1;
+}
+
+#define CODE_BREAK_NUM 6
+#define CODE_BREAK_LOW 0x01
+#define CODE_BREAK_HIGH 0x02
+
+struct code_hw_breakpoint {
+ stm32_addr_t addr;
+ int type;
+};
+
+struct code_hw_breakpoint code_breaks[CODE_BREAK_NUM];
+
+static void init_code_breakpoints(struct stlink* sl) {
+ memset(sl->q_buf, 0, 4);
+ sl->q_buf[0] = 0x03; // KEY | ENABLE
+ stlink_write_mem32(sl, 0xe0002000, 4);
+
+ memset(sl->q_buf, 0, 4);
+ for(int i = 0; i < CODE_BREAK_NUM; i++) {
+ code_breaks[i].type = 0;
+ stlink_write_mem32(sl, 0xe0002008 + i * 4, 4);
+ }
+}
+
+static int update_code_breakpoint(struct stlink* sl, stm32_addr_t addr, int set) {
+ stm32_addr_t fpb_addr = addr & ~0x3;
+ int type = addr & 0x2 ? CODE_BREAK_HIGH : CODE_BREAK_LOW;
+
+ if(addr & 1) {
+ fprintf(stderr, "update_code_breakpoint: unaligned address %08x\n", addr);
+ return -1;
+ }
+
+ int id = -1;
+ for(int i = 0; i < CODE_BREAK_NUM; i++) {
+ if(fpb_addr == code_breaks[i].addr ||
+ (set && code_breaks[i].type == 0)) {
+ id = i;
+ break;
+ }
+ }
+
+ if(id == -1) {
+ if(set) return -1; // Free slot not found
+ else return 0; // Breakpoint is already removed
+ }
+
+ struct code_hw_breakpoint* brk = &code_breaks[id];
+
+ brk->addr = fpb_addr;
+
+ if(set) brk->type |= type;
+ else brk->type &= ~type;
+
+ memset(sl->q_buf, 0, 4);
+
+ if(brk->type == 0) {
+ #ifdef DEBUG
+ printf("clearing hw break %d\n", id);
+ #endif
+
+ stlink_write_mem32(sl, 0xe0002008 + id * 4, 4);
+ } else {
+ sl->q_buf[0] = ( brk->addr & 0xff) | 1;
+ sl->q_buf[1] = ((brk->addr >> 8) & 0xff);
+ sl->q_buf[2] = ((brk->addr >> 16) & 0xff);
+ sl->q_buf[3] = ((brk->addr >> 24) & 0xff) | (brk->type << 6);
+
+ #ifdef DEBUG
+ printf("setting hw break %d at %08x (%d)\n",
+ id, brk->addr, brk->type);
+ printf("reg %02x %02x %02x %02x\n",
+ sl->q_buf[3], sl->q_buf[2], sl->q_buf[1], sl->q_buf[0]);
+ #endif
+
+ stlink_write_mem32(sl, 0xe0002008 + id * 4, 4);
+ }
+
+ return 0;
+}
+
+
+struct flash_block {
+ stm32_addr_t addr;
+ unsigned length;
+ uint8_t* data;
+
+ struct flash_block* next;
+};
+
+static struct flash_block* flash_root;
+
+static int flash_add_block(stm32_addr_t addr, unsigned length,
+ struct stlink* sl) {
+ if(addr < FLASH_BASE || addr + length > FLASH_BASE + FLASH_SIZE) {
+ fprintf(stderr, "flash_add_block: incorrect bounds\n");
+ return -1;
+ }
+
+ if(addr % FLASH_PAGE != 0 || length % FLASH_PAGE != 0) {
+ fprintf(stderr, "flash_add_block: unaligned block\n");
+ return -1;
+ }
+
+ struct flash_block* new = malloc(sizeof(struct flash_block));
+ new->next = flash_root;
+
+ new->addr = addr;
+ new->length = length;
+ new->data = calloc(length, 1);
+
+ flash_root = new;
+
+ return 0;
+}
+
+static int flash_populate(stm32_addr_t addr, uint8_t* data, unsigned length) {
+ int fit_blocks = 0, fit_length = 0;
+
+ for(struct flash_block* fb = flash_root; fb; fb = fb->next) {
+ /* Block: ------X------Y--------
+ * Data: a-----b
+ * a--b
+ * a-----------b
+ * Block intersects with data, if:
+ * a < Y && b > x
+ */
+
+ unsigned X = fb->addr, Y = fb->addr + fb->length;
+ unsigned a = addr, b = addr + length;
+ if(a < Y && b > X) {
+ // from start of the block
+ unsigned start = (a > X ? a : X) - X;
+ unsigned end = (b > Y ? Y : b) - X;
+
+ memcpy(fb->data + start, data, end - start);
+
+ fit_blocks++;
+ fit_length += end - start;
+ }
+ }
+
+ if(fit_blocks == 0) {
+ fprintf(stderr, "Unfit data block %08x -> %04x\n", addr, length);
+ return -1;
+ }
+
+ if(fit_length != length) {
+ fprintf(stderr, "warning: data block %08x -> %04x truncated to %04x\n",
+ addr, length, fit_length);
+ fprintf(stderr, "(this is not an error, just a GDB glitch)\n");
+ }
+
+ return 0;
+}
+
+static int flash_go(struct stlink* sl) {
+ int error = -1;
+
+ // Some kinds of clock settings do not allow writing to flash.
+ stlink_reset(sl);
+
+ for(struct flash_block* fb = flash_root; fb; fb = fb->next) {
+ #ifdef DEBUG
+ printf("flash_do: block %08x -> %04x\n", fb->addr, fb->length);
+ #endif
+
+ unsigned length = fb->length;
+ for(stm32_addr_t page = fb->addr; page < fb->addr + fb->length; page += FLASH_PAGE) {
+ #ifdef DEBUG
+ printf("flash_do: page %08x\n", page);
+ #endif
+
+ stlink_erase_flash_page(sl, page);
+
+ if(stlink_write_flash(sl, page, fb->data + (page - fb->addr),
+ length > FLASH_PAGE ? FLASH_PAGE : length) < 0)
+ goto error;
+ }
+
+ }
+
+ stlink_reset(sl);
+
+ error = 0;
+
+error:
+ for(struct flash_block* fb = flash_root, *next; fb; fb = next) {
+ next = fb->next;
+ free(fb->data);
+ free(fb);
+ }
+
+ flash_root = NULL;
+
+ return error;
+}
+
int serve(struct stlink* sl, int port) {
int sock = socket(AF_INET, SOCK_STREAM, 0);
if(sock < 0) {
stlink_force_debug(sl);
stlink_reset(sl);
+ init_code_breakpoints(sl);
+ init_data_watchpoints(sl);
printf("Listening at *:%d...\n", port);
printf("GDB connected.\n");
+ /*
+ * To allow resetting the chip from GDB it is required to
+ * emulate attaching and detaching to target.
+ */
+ unsigned int attached = 1;
+
while(1) {
char* packet;
const char* data = NULL;
if(!strcmp(type, "memory-map") && !strcmp(op, "read"))
- data = c_memory_map;
+ data = current_memory_map;
if(data) {
unsigned data_length = strlen(data);
}
case 'v': {
- char *separator = strstr(packet, ":"), *params = "";
- if(separator == NULL) {
- separator = packet + strlen(packet);
- } else {
- params = separator + 1;
- }
+ char *params = NULL;
+ char *cmdName = strtok_r(packet, ":;", ¶ms);
- unsigned cmdNameLength = (separator - &packet[1]);
- char* cmdName = calloc(cmdNameLength + 1, 1);
- strncpy(cmdName, &packet[1], cmdNameLength);
+ cmdName++; // vCommand -> Command
if(!strcmp(cmdName, "FlashErase")) {
char *s_addr, *s_length;
addr, length);
#endif
- for(stm32_addr_t cur = addr;
- cur < addr + length; cur += 0x400) {
- #ifdef DEBUG
- printf("do_erase: %08x\n", cur);
- #endif
-
- stlink_erase_flash_page(sl, cur);
+ if(flash_add_block(addr, length, sl) < 0) {
+ reply = strdup("E00");
+ } else {
+ reply = strdup("OK");
}
-
- reply = strdup("OK");
} else if(!strcmp(cmdName, "FlashWrite")) {
char *s_addr, *data;
char *tok = params;
printf("binary packet %d -> %d\n", data_length, dec_index);
#endif
- if(!stlink_write_flash(sl, addr, decoded, dec_index) < 0) {
- fprintf(stderr, "Flash write or verification failed.\n");
+ if(flash_populate(addr, decoded, dec_index) < 0) {
reply = strdup("E00");
} else {
reply = strdup("OK");
}
} else if(!strcmp(cmdName, "FlashDone")) {
- stlink_reset(sl);
+ if(flash_go(sl) < 0) {
+ reply = strdup("E00");
+ } else {
+ reply = strdup("OK");
+ }
+ } else if(!strcmp(cmdName, "Kill")) {
+ attached = 0;
reply = strdup("OK");
}
if(reply == NULL)
reply = strdup("");
- free(cmdName);
-
break;
}
case 'c':
stlink_run(sl);
- printf("Core running, waiting for interrupt (either in chip or GDB).\n");
-
while(1) {
int status = gdb_check_for_interrupt(client);
if(status < 0) {
break;
}
- usleep(200000);
+ usleep(100000);
}
reply = strdup("S05"); // TRAP
break;
case '?':
- reply = strdup("S05"); // TRAP
+ if(attached) {
+ reply = strdup("S05"); // TRAP
+ } else {
+ /* Stub shall reply OK if not attached. */
+ reply = strdup("OK");
+ }
break;
case 'g':
break;
}
- case 'k': {
- // After this function will be entered afterwards, the
- // chip will be reset anyway. So this is a no-op.
+ case 'Z': {
+ char *endptr;
+ stm32_addr_t addr = strtoul(&packet[3], &endptr, 16);
+ stm32_addr_t len = strtoul(&endptr[1], NULL, 16);
- close(client);
- return 0;
+ switch (packet[1]) {
+ case '1':
+ if(update_code_breakpoint(sl, addr, 1) < 0) {
+ reply = strdup("E00");
+ } else {
+ reply = strdup("OK");
+ }
+ break;
+
+ case '2': // insert write watchpoint
+ case '3': // insert read watchpoint
+ case '4': // insert access watchpoint
+ {
+ enum watchfun wf;
+ if(packet[1] == '2') {
+ wf = WATCHWRITE;
+ } else if(packet[1] == '3') {
+ wf = WATCHREAD;
+ } else {
+ wf = WATCHACCESS;
+ if(add_data_watchpoint(sl, wf, addr, len) < 0) {
+ reply = strdup("E00");
+ } else {
+ reply = strdup("OK");
+ break;
+ }
+ }
+ }
+
+ default:
+ reply = strdup("");
+ }
+ break;
+ }
+ case 'z': {
+ char *endptr;
+ stm32_addr_t addr = strtoul(&packet[3], &endptr, 16);
+ stm32_addr_t len = strtoul(&endptr[1], NULL, 16);
+
+ switch (packet[1]) {
+ case '1': // remove breakpoint
+ update_code_breakpoint(sl, addr, 0);
+ reply = strdup("OK");
+ break;
+
+ case '2' : // remove write watchpoint
+ case '3' : // remove read watchpoint
+ case '4' : // remove access watchpoint
+ if(delete_data_watchpoint(sl, addr) < 0) {
+ reply = strdup("E00");
+ } else {
+ reply = strdup("OK");
+ break;
+ }
+
+ default:
+ reply = strdup("");
+ }
+ break;
+ }
+
+ case '!': {
+ /*
+ * Enter extended mode which allows restarting.
+ * We do support that always.
+ */
+
+ reply = strdup("OK");
+
+ break;
+ }
+
+ case 'R': {
+ /* Reset the core. */
+
+ stlink_reset(sl);
+ init_code_breakpoints(sl);
+ init_data_watchpoints(sl);
+
+ attached = 1;
+
+ reply = strdup("OK");
+
+ break;
}
default: