* Copyright (C) 2005 by Dominic Rath *
* Dominic.Rath@gmx.de *
* *
+ * Copyright (C) 2008 by Spencer Oliver *
+ * spen@spen-soft.co.uk *
+ *
+ * Copyright (C) 2008 by Oyvind Harboe *
+ * oyvind.harboe@zylin.com *
+ * *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
#include <string.h>
#include <unistd.h>
-str9x_mem_layout_t mem_layout_str9bank0[] = {
- {0x00000000, 0x10000, 0x01},
- {0x00010000, 0x10000, 0x02},
- {0x00020000, 0x10000, 0x04},
- {0x00030000, 0x10000, 0x08},
- {0x00040000, 0x10000, 0x10},
- {0x00050000, 0x10000, 0x20},
- {0x00060000, 0x10000, 0x40},
- {0x00070000, 0x10000, 0x80},
-};
-
-str9x_mem_layout_t mem_layout_str9bank1[] = {
- {0x00000000, 0x02000, 0x100},
- {0x00002000, 0x02000, 0x200},
- {0x00004000, 0x02000, 0x400},
- {0x00006000, 0x02000, 0x800}
-};
-
static u32 bank1start = 0x00080000;
int str9x_register_commands(struct command_context_s *cmd_ctx);
str9x_flash_bank_t *str9x_info = bank->driver_priv;
int i;
- int num_sectors = 0;
+ int num_sectors;
int b0_sectors = 0, b1_sectors = 0;
-
+ u32 offset = 0;
+
+ /* set if we have large flash str9 */
+ str9x_info->variant = 0;
+ str9x_info->bank1 = 0;
+
switch (bank->size)
{
case (256 * 1024):
case (512 * 1024):
b0_sectors = 8;
break;
+ case (1024 * 1024):
+ bank1start = 0x00100000;
+ str9x_info->variant = 1;
+ b0_sectors = 16;
+ break;
+ case (2048 * 1024):
+ bank1start = 0x00200000;
+ str9x_info->variant = 1;
+ b0_sectors = 32;
+ break;
+ case (128 * 1024):
+ str9x_info->variant = 1;
+ str9x_info->bank1 = 1;
+ b1_sectors = 8;
+ bank1start = bank->base;
+ break;
case (32 * 1024):
+ str9x_info->bank1 = 1;
b1_sectors = 4;
bank1start = bank->base;
break;
for (i = 0; i < b0_sectors; i++)
{
- bank->sectors[num_sectors].offset = mem_layout_str9bank0[i].sector_start;
- bank->sectors[num_sectors].size = mem_layout_str9bank0[i].sector_size;
+ bank->sectors[num_sectors].offset = offset;
+ bank->sectors[num_sectors].size = 0x10000;
+ offset += bank->sectors[i].size;
bank->sectors[num_sectors].is_erased = -1;
bank->sectors[num_sectors].is_protected = 1;
- str9x_info->sector_bits[num_sectors++] = mem_layout_str9bank0[i].sector_bit;
+ str9x_info->sector_bits[num_sectors++] = (1<<i);
}
for (i = 0; i < b1_sectors; i++)
{
- bank->sectors[num_sectors].offset = mem_layout_str9bank1[i].sector_start;
- bank->sectors[num_sectors].size = mem_layout_str9bank1[i].sector_size;
+ bank->sectors[num_sectors].offset = offset;
+ bank->sectors[num_sectors].size = str9x_info->variant == 0 ? 0x2000 : 0x4000;
+ offset += bank->sectors[i].size;
bank->sectors[num_sectors].is_erased = -1;
bank->sectors[num_sectors].is_protected = 1;
- str9x_info->sector_bits[num_sectors++] = mem_layout_str9bank1[i].sector_bit;
+ if (str9x_info->variant)
+ str9x_info->sector_bits[num_sectors++] = (1<<i);
+ else
+ str9x_info->sector_bits[num_sectors++] = (1<<(i+8));
}
return ERROR_OK;
int str9x_protect_check(struct flash_bank_s *bank)
{
+ int retval;
str9x_flash_bank_t *str9x_info = bank->driver_priv;
target_t *target = bank->target;
int i;
u32 adr;
- u16 status;
+ u32 status = 0;
if (bank->target->state != TARGET_HALTED)
{
+ LOG_ERROR("Target not halted");
return ERROR_TARGET_NOT_HALTED;
}
/* read level one protection */
- adr = bank1start + 0x10;
+ if (str9x_info->variant)
+ {
+ if (str9x_info->bank1)
+ {
+ adr = bank1start + 0x18;
+ if ((retval=target_write_u16(target, adr, 0x90))!=ERROR_OK)
+ {
+ return retval;
+ }
+ if ((retval=target_read_u16(target, adr, (u16*)&status))!=ERROR_OK)
+ {
+ return retval;
+ }
+ }
+ else
+ {
+ adr = bank1start + 0x14;
+ if ((retval=target_write_u16(target, adr, 0x90))!=ERROR_OK)
+ {
+ return retval;
+ }
+ if ((retval=target_read_u32(target, adr, &status))!=ERROR_OK)
+ {
+ return retval;
+ }
+ }
+ }
+ else
+ {
+ adr = bank1start + 0x10;
+ if ((retval=target_write_u16(target, adr, 0x90))!=ERROR_OK)
+ {
+ return retval;
+ }
+ if ((retval=target_read_u16(target, adr, (u16*)&status))!=ERROR_OK)
+ {
+ return retval;
+ }
+ }
- target_write_u16(target, adr, 0x90);
- target_read_u16(target, adr, &status);
- target_write_u16(target, adr, 0xFF);
+ /* read array command */
+ if ((retval=target_write_u16(target, adr, 0xFF))!=ERROR_OK)
+ {
+ return retval;
+ }
for (i = 0; i < bank->num_sectors; i++)
{
int i;
u32 adr;
u8 status;
+ u8 erase_cmd;
if (bank->target->state != TARGET_HALTED)
{
+ LOG_ERROR("Target not halted");
return ERROR_TARGET_NOT_HALTED;
}
+ /* Check if we erase whole bank */
+ if ((first == 0) && (last == (bank->num_sectors - 1)))
+ {
+ /* Optimize to run erase bank command instead of sector */
+ erase_cmd = 0x80;
+ }
+ else
+ {
+ /* Erase sector command */
+ erase_cmd = 0x20;
+ }
+
for (i = first; i <= last; i++)
{
+ int retval;
adr = bank->base + bank->sectors[i].offset;
/* erase sectors */
- target_write_u16(target, adr, 0x20);
- target_write_u16(target, adr, 0xD0);
+ if ((retval=target_write_u16(target, adr, erase_cmd))!=ERROR_OK)
+ {
+ return retval;
+ }
+ if ((retval=target_write_u16(target, adr, 0xD0))!=ERROR_OK)
+ {
+ return retval;
+ }
/* get status */
- target_write_u16(target, adr, 0x70);
-
- while (1) {
- target_read_u8(target, adr, &status);
+ if ((retval=target_write_u16(target, adr, 0x70))!=ERROR_OK)
+ {
+ return retval;
+ }
+
+ int timeout;
+ for (timeout=0; timeout<1000; timeout++) {
+ if ((retval=target_read_u8(target, adr, &status))!=ERROR_OK)
+ {
+ return retval;
+ }
if( status & 0x80 )
break;
- usleep(1000);
+ alive_sleep(1);
+ }
+ if (timeout==1000)
+ {
+ LOG_ERROR("erase timed out");
+ return ERROR_FAIL;
}
/* clear status, also clear read array */
- target_write_u16(target, adr, 0x50);
+ if ((retval=target_write_u16(target, adr, 0x50))!=ERROR_OK)
+ {
+ return retval;
+ }
/* read array command */
- target_write_u16(target, adr, 0xFF);
+ if ((retval=target_write_u16(target, adr, 0xFF))!=ERROR_OK)
+ {
+ return retval;
+ }
if( status & 0x22 )
{
LOG_ERROR("error erasing flash bank, status: 0x%x", status);
return ERROR_FLASH_OPERATION_FAILED;
}
+
+ /* If we ran erase bank command, we are finished */
+ if (erase_cmd == 0x80)
+ break;
}
for (i = first; i <= last; i++)
if (bank->target->state != TARGET_HALTED)
{
+ LOG_ERROR("Target not halted");
return ERROR_TARGET_NOT_HALTED;
}
/* query status */
target_read_u8(target, adr, &status);
+
+ /* clear status, also clear read array */
+ target_write_u16(target, adr, 0x50);
+
+ /* read array command */
+ target_write_u16(target, adr, 0xFF);
}
return ERROR_OK;
u32 address = bank->base + offset;
reg_param_t reg_params[4];
armv4_5_algorithm_t armv4_5_info;
- int retval;
+ int retval = ERROR_OK;
u32 str9x_flash_write_code[] = {
/* write: */
if ((retval = target->type->run_algorithm(target, 0, NULL, 4, reg_params, str9x_info->write_algorithm->address, str9x_info->write_algorithm->address + (18 * 4), 10000, &armv4_5_info)) != ERROR_OK)
{
- target_free_working_area(target, source);
- target_free_working_area(target, str9x_info->write_algorithm);
LOG_ERROR("error executing str9x flash write algorithm");
- return ERROR_FLASH_OPERATION_FAILED;
+ retval = ERROR_FLASH_OPERATION_FAILED;
+ break;
}
if (buf_get_u32(reg_params[3].value, 0, 32) != 0x80)
{
- return ERROR_FLASH_OPERATION_FAILED;
+ retval = ERROR_FLASH_OPERATION_FAILED;
+ break;
}
buffer += thisrun_count * 2;
destroy_reg_param(®_params[2]);
destroy_reg_param(®_params[3]);
- return ERROR_OK;
+ return retval;
}
int str9x_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
if (bank->target->state != TARGET_HALTED)
{
+ LOG_ERROR("Target not halted");
return ERROR_TARGET_NOT_HALTED;
}
/* get status command */
target_write_u16(target, bank_adr, 0x70);
-
- while (1) {
+
+ int timeout;
+ for (timeout=0; timeout<1000; timeout++)
+ {
target_read_u8(target, bank_adr, &status);
if( status & 0x80 )
break;
- usleep(1000);
+ alive_sleep(1);
+ }
+ if (timeout==1000)
+ {
+ LOG_ERROR("write timed out");
+ return ERROR_FAIL;
}
/* clear status reg and read array */
/* query status command */
target_write_u16(target, bank_adr, 0x70);
- while (1) {
+ int timeout;
+ for (timeout=0; timeout<1000; timeout++)
+ {
target_read_u8(target, bank_adr, &status);
if( status & 0x80 )
break;
- usleep(1000);
+ alive_sleep(1);
+ }
+ if (timeout==1000)
+ {
+ LOG_ERROR("write timed out");
+ return ERROR_FAIL;
}
/* clear status reg and read array */
if (bank->target->state != TARGET_HALTED)
{
+ LOG_ERROR("Target not halted");
return ERROR_TARGET_NOT_HALTED;
}
projects / fw / openocd / blobdiff