#include "config.h"
#endif
-#include "replacements.h"
-
#include "str9x.h"
-#include "flash.h"
-#include "target.h"
-#include "log.h"
-#include "armv4_5.h"
#include "arm966e.h"
-#include "algorithm.h"
-#include "binarybuffer.h"
-#include <stdlib.h>
-#include <string.h>
-#include <unistd.h>
-static u32 bank1start = 0x00080000;
+static uint32_t bank1start = 0x00080000;
-int str9x_register_commands(struct command_context_s *cmd_ctx);
-int str9x_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
-int str9x_erase(struct flash_bank_s *bank, int first, int last);
-int str9x_protect(struct flash_bank_s *bank, int set, int first, int last);
-int str9x_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);
-int str9x_probe(struct flash_bank_s *bank);
-int str9x_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
-int str9x_protect_check(struct flash_bank_s *bank);
-int str9x_info(struct flash_bank_s *bank, char *buf, int buf_size);
+static int str9x_register_commands(struct command_context_s *cmd_ctx);
+static int str9x_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
+static int str9x_erase(struct flash_bank_s *bank, int first, int last);
+static int str9x_protect(struct flash_bank_s *bank, int set, int first, int last);
+static int str9x_write(struct flash_bank_s *bank, uint8_t *buffer, uint32_t offset, uint32_t count);
+static int str9x_probe(struct flash_bank_s *bank);
+//static int str9x_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
+static int str9x_protect_check(struct flash_bank_s *bank);
+static int str9x_info(struct flash_bank_s *bank, char *buf, int buf_size);
-int str9x_handle_flash_config_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
+static int str9x_handle_flash_config_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
flash_driver_t str9x_flash =
{
.info = str9x_info
};
-int str9x_register_commands(struct command_context_s *cmd_ctx)
+static int str9x_register_commands(struct command_context_s *cmd_ctx)
{
command_t *str9x_cmd = register_command(cmd_ctx, NULL, "str9x", NULL, COMMAND_ANY, NULL);
-
+
register_command(cmd_ctx, str9x_cmd, "flash_config", str9x_handle_flash_config_command, COMMAND_EXEC,
"configure str9 flash controller");
-
+
return ERROR_OK;
}
-int str9x_build_block_list(struct flash_bank_s *bank)
+static int str9x_build_block_list(struct flash_bank_s *bank)
{
str9x_flash_bank_t *str9x_info = bank->driver_priv;
-
+
int i;
int num_sectors;
int b0_sectors = 0, b1_sectors = 0;
- u32 offset = 0;
-
+ uint32_t offset = 0;
+
/* set if we have large flash str9 */
str9x_info->variant = 0;
str9x_info->bank1 = 0;
-
+
switch (bank->size)
{
case (256 * 1024):
LOG_ERROR("BUG: unknown bank->size encountered");
exit(-1);
}
-
+
num_sectors = b0_sectors + b1_sectors;
-
+
bank->num_sectors = num_sectors;
bank->sectors = malloc(sizeof(flash_sector_t) * num_sectors);
- str9x_info->sector_bits = malloc(sizeof(u32) * num_sectors);
-
+ str9x_info->sector_bits = malloc(sizeof(uint32_t) * num_sectors);
+
num_sectors = 0;
-
+
for (i = 0; i < b0_sectors; i++)
{
bank->sectors[num_sectors].offset = offset;
else
str9x_info->sector_bits[num_sectors++] = (1<<(i+8));
}
-
+
return ERROR_OK;
}
/* flash bank str9x <base> <size> 0 0 <target#>
*/
-int str9x_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank)
+static int str9x_flash_bank_command(struct command_context_s *cmd_ctx,
+ char *cmd, char **args, int argc, struct flash_bank_s *bank)
{
str9x_flash_bank_t *str9x_info;
-
+
if (argc < 6)
{
LOG_WARNING("incomplete flash_bank str9x configuration");
return ERROR_FLASH_BANK_INVALID;
}
-
+
str9x_info = malloc(sizeof(str9x_flash_bank_t));
bank->driver_priv = str9x_info;
-
+
str9x_build_block_list(bank);
-
+
str9x_info->write_algorithm = NULL;
-
+
return ERROR_OK;
}
-int str9x_protect_check(struct flash_bank_s *bank)
+static int str9x_protect_check(struct flash_bank_s *bank)
{
int retval;
str9x_flash_bank_t *str9x_info = bank->driver_priv;
target_t *target = bank->target;
-
+
int i;
- u32 adr;
- u32 status = 0;
+ uint32_t adr;
+ uint32_t status = 0;
+ uint16_t hstatus = 0;
if (bank->target->state != TARGET_HALTED)
{
}
/* read level one protection */
-
+
if (str9x_info->variant)
{
if (str9x_info->bank1)
{
return retval;
}
- if ((retval=target_read_u16(target, adr, (u16*)&status))!=ERROR_OK)
+ if ((retval=target_read_u16(target, adr, &hstatus))!=ERROR_OK)
{
return retval;
}
+ status = hstatus;
}
else
{
{
return retval;
}
- if ((retval=target_read_u16(target, adr, (u16*)&status))!=ERROR_OK)
+ if ((retval=target_read_u16(target, adr, &hstatus))!=ERROR_OK)
{
return retval;
}
+ status = hstatus;
}
-
+
/* read array command */
if ((retval=target_write_u16(target, adr, 0xFF))!=ERROR_OK)
{
return retval;
}
-
+
for (i = 0; i < bank->num_sectors; i++)
{
if (status & str9x_info->sector_bits[i])
else
bank->sectors[i].is_protected = 0;
}
-
+
return ERROR_OK;
}
-int str9x_erase(struct flash_bank_s *bank, int first, int last)
+static int str9x_erase(struct flash_bank_s *bank, int first, int last)
{
target_t *target = bank->target;
int i;
- u32 adr;
- u8 status;
- u8 erase_cmd;
-
+ uint32_t adr;
+ uint8_t status;
+ uint8_t erase_cmd;
+
if (bank->target->state != TARGET_HALTED)
{
LOG_ERROR("Target not halted");
/* Erase sector command */
erase_cmd = 0x20;
}
-
+
for (i = first; i <= last; i++)
{
int retval;
adr = bank->base + bank->sectors[i].offset;
-
+
/* erase sectors */
if ((retval=target_write_u16(target, adr, erase_cmd))!=ERROR_OK)
{
{
return retval;
}
-
+
/* get status */
if ((retval=target_write_u16(target, adr, 0x70))!=ERROR_OK)
{
return retval;
}
-
- while (1) {
+
+ int timeout;
+ for (timeout=0; timeout<1000; timeout++) {
if ((retval=target_read_u8(target, adr, &status))!=ERROR_OK)
{
return retval;
}
- if( status & 0x80 )
+ if ( status & 0x80 )
break;
alive_sleep(1);
}
-
+ if (timeout==1000)
+ {
+ LOG_ERROR("erase timed out");
+ return ERROR_FAIL;
+ }
+
/* clear status, also clear read array */
if ((retval=target_write_u16(target, adr, 0x50))!=ERROR_OK)
{
return retval;
}
-
+
/* read array command */
if ((retval=target_write_u16(target, adr, 0xFF))!=ERROR_OK)
{
return retval;
}
-
- if( status & 0x22 )
+
+ if ( status & 0x22 )
{
LOG_ERROR("error erasing flash bank, status: 0x%x", status);
return ERROR_FLASH_OPERATION_FAILED;
}
-
+
/* If we ran erase bank command, we are finished */
if (erase_cmd == 0x80)
break;
}
-
+
for (i = first; i <= last; i++)
bank->sectors[i].is_erased = 1;
return ERROR_OK;
}
-int str9x_protect(struct flash_bank_s *bank, int set, int first, int last)
+static int str9x_protect(struct flash_bank_s *bank,
+ int set, int first, int last)
{
target_t *target = bank->target;
int i;
- u32 adr;
- u8 status;
-
+ uint32_t adr;
+ uint8_t status;
+
if (bank->target->state != TARGET_HALTED)
{
LOG_ERROR("Target not halted");
return ERROR_TARGET_NOT_HALTED;
}
-
+
for (i = first; i <= last; i++)
{
/* Level One Protection */
-
+
adr = bank->base + bank->sectors[i].offset;
-
+
target_write_u16(target, adr, 0x60);
- if( set )
+ if ( set )
target_write_u16(target, adr, 0x01);
else
target_write_u16(target, adr, 0xD0);
-
+
/* query status */
target_read_u8(target, adr, &status);
-
+
/* clear status, also clear read array */
target_write_u16(target, adr, 0x50);
-
+
/* read array command */
target_write_u16(target, adr, 0xFF);
}
-
+
return ERROR_OK;
}
-int str9x_write_block(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
+static int str9x_write_block(struct flash_bank_s *bank,
+ uint8_t *buffer, uint32_t offset, uint32_t count)
{
str9x_flash_bank_t *str9x_info = bank->driver_priv;
target_t *target = bank->target;
- u32 buffer_size = 8192;
+ uint32_t buffer_size = 8192;
working_area_t *source;
- u32 address = bank->base + offset;
+ uint32_t address = bank->base + offset;
reg_param_t reg_params[4];
armv4_5_algorithm_t armv4_5_info;
int retval = ERROR_OK;
-
- u32 str9x_flash_write_code[] = {
+
+ uint32_t str9x_flash_write_code[] = {
/* write: */
0xe3c14003, /* bic r4, r1, #3 */
0xe3a03040, /* mov r3, #0x40 */
/* exit: */
0xeafffffe, /* b exit */
};
-
+
/* flash write code */
if (target_alloc_working_area(target, 4 * 19, &str9x_info->write_algorithm) != ERROR_OK)
{
LOG_WARNING("no working area available, can't do block memory writes");
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
};
-
- target_write_buffer(target, str9x_info->write_algorithm->address, 19 * 4, (u8*)str9x_flash_write_code);
+
+ target_write_buffer(target, str9x_info->write_algorithm->address, 19 * 4, (uint8_t*)str9x_flash_write_code);
/* memory buffer */
while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)
/* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
if (str9x_info->write_algorithm)
target_free_working_area(target, str9x_info->write_algorithm);
-
+
LOG_WARNING("no large enough working area available, can't do block memory writes");
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
}
-
+
armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
armv4_5_info.core_state = ARMV4_5_STATE_ARM;
-
+
init_reg_param(®_params[0], "r0", 32, PARAM_OUT);
init_reg_param(®_params[1], "r1", 32, PARAM_OUT);
init_reg_param(®_params[2], "r2", 32, PARAM_OUT);
init_reg_param(®_params[3], "r3", 32, PARAM_IN);
-
+
while (count > 0)
{
- u32 thisrun_count = (count > (buffer_size / 2)) ? (buffer_size / 2) : count;
-
+ uint32_t thisrun_count = (count > (buffer_size / 2)) ? (buffer_size / 2) : count;
+
target_write_buffer(target, source->address, thisrun_count * 2, buffer);
-
+
buf_set_u32(reg_params[0].value, 0, 32, source->address);
buf_set_u32(reg_params[1].value, 0, 32, address);
buf_set_u32(reg_params[2].value, 0, 32, thisrun_count);
- if ((retval = target->type->run_algorithm(target, 0, NULL, 4, reg_params, str9x_info->write_algorithm->address, str9x_info->write_algorithm->address + (18 * 4), 10000, &armv4_5_info)) != ERROR_OK)
+ if ((retval = target_run_algorithm(target, 0, NULL, 4, reg_params, str9x_info->write_algorithm->address, str9x_info->write_algorithm->address + (18 * 4), 10000, &armv4_5_info)) != ERROR_OK)
{
LOG_ERROR("error executing str9x flash write algorithm");
retval = ERROR_FLASH_OPERATION_FAILED;
break;
}
-
+
if (buf_get_u32(reg_params[3].value, 0, 32) != 0x80)
{
retval = ERROR_FLASH_OPERATION_FAILED;
break;
}
-
+
buffer += thisrun_count * 2;
address += thisrun_count * 2;
count -= thisrun_count;
}
-
+
target_free_working_area(target, source);
target_free_working_area(target, str9x_info->write_algorithm);
-
+
destroy_reg_param(®_params[0]);
destroy_reg_param(®_params[1]);
destroy_reg_param(®_params[2]);
destroy_reg_param(®_params[3]);
-
+
return retval;
}
-int str9x_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
+static int str9x_write(struct flash_bank_s *bank,
+ uint8_t *buffer, uint32_t offset, uint32_t count)
{
target_t *target = bank->target;
- u32 words_remaining = (count / 2);
- u32 bytes_remaining = (count & 0x00000001);
- u32 address = bank->base + offset;
- u32 bytes_written = 0;
- u8 status;
- u32 retval;
- u32 check_address = offset;
- u32 bank_adr;
+ uint32_t words_remaining = (count / 2);
+ uint32_t bytes_remaining = (count & 0x00000001);
+ uint32_t address = bank->base + offset;
+ uint32_t bytes_written = 0;
+ uint8_t status;
+ int retval;
+ uint32_t check_address = offset;
+ uint32_t bank_adr;
int i;
-
+
if (bank->target->state != TARGET_HALTED)
{
LOG_ERROR("Target not halted");
if (offset & 0x1)
{
- LOG_WARNING("offset 0x%x breaks required 2-byte alignment", offset);
+ LOG_WARNING("offset 0x%" PRIx32 " breaks required 2-byte alignment", offset);
return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
}
-
+
for (i = 0; i < bank->num_sectors; i++)
{
- u32 sec_start = bank->sectors[i].offset;
- u32 sec_end = sec_start + bank->sectors[i].size;
-
+ uint32_t sec_start = bank->sectors[i].offset;
+ uint32_t sec_end = sec_start + bank->sectors[i].size;
+
/* check if destination falls within the current sector */
if ((check_address >= sec_start) && (check_address < sec_end))
{
check_address = sec_end;
}
}
-
+
if (check_address != offset + count)
return ERROR_FLASH_DST_OUT_OF_BANK;
-
+
/* multiple half words (2-byte) to be programmed? */
- if (words_remaining > 0)
+ if (words_remaining > 0)
{
/* try using a block write */
if ((retval = str9x_write_block(bank, buffer, offset, words_remaining)) != ERROR_OK)
if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
{
/* if block write failed (no sufficient working area),
- * we use normal (slow) single dword accesses */
+ * we use normal (slow) single dword accesses */
LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
}
else if (retval == ERROR_FLASH_OPERATION_FAILED)
while (words_remaining > 0)
{
bank_adr = address & ~0x03;
-
+
/* write data command */
target_write_u16(target, bank_adr, 0x40);
- target->type->write_memory(target, address, 2, 1, buffer + bytes_written);
-
+ target_write_memory(target, address, 2, 1, buffer + bytes_written);
+
/* get status command */
target_write_u16(target, bank_adr, 0x70);
-
- while (1) {
+
+ int timeout;
+ for (timeout=0; timeout<1000; timeout++)
+ {
target_read_u8(target, bank_adr, &status);
- if( status & 0x80 )
+ if ( status & 0x80 )
break;
alive_sleep(1);
}
-
+ if (timeout==1000)
+ {
+ LOG_ERROR("write timed out");
+ return ERROR_FAIL;
+ }
+
/* clear status reg and read array */
target_write_u16(target, bank_adr, 0x50);
target_write_u16(target, bank_adr, 0xFF);
-
+
if (status & 0x10)
return ERROR_FLASH_OPERATION_FAILED;
else if (status & 0x02)
words_remaining--;
address += 2;
}
-
+
if (bytes_remaining)
{
- u8 last_halfword[2] = {0xff, 0xff};
+ uint8_t last_halfword[2] = {0xff, 0xff};
int i = 0;
-
- while(bytes_remaining > 0)
+
+ while (bytes_remaining > 0)
{
- last_halfword[i++] = *(buffer + bytes_written);
+ last_halfword[i++] = *(buffer + bytes_written);
bytes_remaining--;
bytes_written++;
}
-
+
bank_adr = address & ~0x03;
-
- /* write data comamnd */
+
+ /* write data command */
target_write_u16(target, bank_adr, 0x40);
- target->type->write_memory(target, address, 2, 1, last_halfword);
-
+ target_write_memory(target, address, 2, 1, last_halfword);
+
/* query status command */
target_write_u16(target, bank_adr, 0x70);
-
- while (1) {
+
+ int timeout;
+ for (timeout=0; timeout<1000; timeout++)
+ {
target_read_u8(target, bank_adr, &status);
- if( status & 0x80 )
+ if ( status & 0x80 )
break;
alive_sleep(1);
}
-
+ if (timeout==1000)
+ {
+ LOG_ERROR("write timed out");
+ return ERROR_FAIL;
+ }
+
/* clear status reg and read array */
target_write_u16(target, bank_adr, 0x50);
target_write_u16(target, bank_adr, 0xFF);
-
+
if (status & 0x10)
return ERROR_FLASH_OPERATION_FAILED;
else if (status & 0x02)
return ERROR_FLASH_OPERATION_FAILED;
}
-
+
return ERROR_OK;
}
-int str9x_probe(struct flash_bank_s *bank)
+static int str9x_probe(struct flash_bank_s *bank)
{
return ERROR_OK;
}
-int str9x_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
+#if 0
+static int str9x_handle_part_id_command(struct command_context_s *cmd_ctx,
+ char *cmd, char **args, int argc)
{
return ERROR_OK;
}
+#endif
-int str9x_info(struct flash_bank_s *bank, char *buf, int buf_size)
+static int str9x_info(struct flash_bank_s *bank, char *buf, int buf_size)
{
snprintf(buf, buf_size, "str9x flash driver info" );
return ERROR_OK;
}
-int str9x_handle_flash_config_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
+static int str9x_handle_flash_config_command(struct command_context_s *cmd_ctx,
+ char *cmd, char **args, int argc)
{
str9x_flash_bank_t *str9x_info;
flash_bank_t *bank;
target_t *target = NULL;
-
+
if (argc < 5)
{
return ERROR_COMMAND_SYNTAX_ERROR;
}
-
+
bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
if (!bank)
{
command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
return ERROR_OK;
}
-
+
str9x_info = bank->driver_priv;
-
+
target = bank->target;
-
+
if (bank->target->state != TARGET_HALTED)
{
LOG_ERROR("Target not halted");
return ERROR_TARGET_NOT_HALTED;
}
-
+
/* config flash controller */
target_write_u32(target, FLASH_BBSR, strtoul(args[1], NULL, 0));
target_write_u32(target, FLASH_NBBSR, strtoul(args[2], NULL, 0));
/* set bit 18 instruction TCM order as per flash programming manual */
arm966e_write_cp15(target, 62, 0x40000);
-
+
/* enable flash bank 1 */
target_write_u32(target, FLASH_CR, 0x18);
return ERROR_OK;
projects / fw / openocd / blobdiff