refactor handle_flash_bank_command

[fw/openocd] / src / flash / s3c2440_nand.c

diff --git a/src/flash/s3c2440_nand.c b/src/flash/s3c2440_nand.c
index 80020f63def9ed1601f1f34f4554cec7834c8b57..65e5a51180d6bba843a4e3ea41cc7eacdbe07345 100644 (file)
--- a/src/flash/s3c2440_nand.c
+++ b/src/flash/s3c2440_nand.c
@@ -33,7 +33,7 @@
 
 NAND_DEVICE_COMMAND_HANDLER(s3c2440_nand_device_command)
 {
-       s3c24xx_nand_controller_t *info;
+       struct s3c24xx_nand_controller *info;
        CALL_S3C24XX_DEVICE_COMMAND(nand, &info);
 
        /* fill in the address fields for the core device */
@@ -45,10 +45,10 @@ NAND_DEVICE_COMMAND_HANDLER(s3c2440_nand_device_command)
        return ERROR_OK;
 }
 
-static int s3c2440_init(struct nand_device_s *nand)
+static int s3c2440_init(struct nand_device *nand)
 {
-       s3c24xx_nand_controller_t *s3c24xx_info = nand->controller_priv;
-       target_t *target = s3c24xx_info->target;
+       struct s3c24xx_nand_controller *s3c24xx_info = nand->controller_priv;
+       struct target *target = s3c24xx_info->target;
 
        target_write_u32(target, S3C2410_NFCONF,
                         S3C2440_NFCONF_TACLS(3) |
@@ -61,10 +61,10 @@ static int s3c2440_init(struct nand_device_s *nand)
        return ERROR_OK;
 }
 
-int s3c2440_nand_ready(struct nand_device_s *nand, int timeout)
+int s3c2440_nand_ready(struct nand_device *nand, int timeout)
 {
-       s3c24xx_nand_controller_t *s3c24xx_info = nand->controller_priv;
-       target_t *target = s3c24xx_info->target;
+       struct s3c24xx_nand_controller *s3c24xx_info = nand->controller_priv;
+       struct target *target = s3c24xx_info->target;
        uint8_t status;
 
        if (target->state != TARGET_HALTED) {
@@ -87,10 +87,10 @@ int s3c2440_nand_ready(struct nand_device_s *nand, int timeout)
 
 /* use the fact we can read/write 4 bytes in one go via a single 32bit op */
 
-int s3c2440_read_block_data(struct nand_device_s *nand, uint8_t *data, int data_size)
+int s3c2440_read_block_data(struct nand_device *nand, uint8_t *data, int data_size)
 {
-       s3c24xx_nand_controller_t *s3c24xx_info = nand->controller_priv;
-       target_t *target = s3c24xx_info->target;
+       struct s3c24xx_nand_controller *s3c24xx_info = nand->controller_priv;
+       struct target *target = s3c24xx_info->target;
        uint32_t nfdata = s3c24xx_info->data;
        uint32_t tmp;
 
@@ -123,10 +123,10 @@ int s3c2440_read_block_data(struct nand_device_s *nand, uint8_t *data, int data_
        return ERROR_OK;
 }
 
-int s3c2440_write_block_data(struct nand_device_s *nand, uint8_t *data, int data_size)
+int s3c2440_write_block_data(struct nand_device *nand, uint8_t *data, int data_size)
 {
-       s3c24xx_nand_controller_t *s3c24xx_info = nand->controller_priv;
-       target_t *target = s3c24xx_info->target;
+       struct s3c24xx_nand_controller *s3c24xx_info = nand->controller_priv;
+       struct target *target = s3c24xx_info->target;
        uint32_t nfdata = s3c24xx_info->data;
        uint32_t tmp;
 
@@ -153,7 +153,7 @@ int s3c2440_write_block_data(struct nand_device_s *nand, uint8_t *data, int data
        return ERROR_OK;
 }
 
-nand_flash_controller_t s3c2440_nand_controller = {
+struct nand_flash_controller s3c2440_nand_controller = {
                .name = "s3c2440",
                .nand_device_command = &s3c2440_nand_device_command,
                .register_commands = &s3c24xx_register_commands,