#include "config.h"
#endif
-#include "replacements.h"
-#include "log.h"
-
-#include <stdlib.h>
-#include <string.h>
-
-#include "nand.h"
-#include "target.h"
+#include "arm_nandio.h"
#include "armv4_5.h"
-#include "binarybuffer.h"
+
typedef struct orion_nand_controller_s
{
struct target_s *target;
- working_area_t *copy_area;
- u32 cmd;
- u32 addr;
- u32 data;
+ struct arm_nand_data io;
+
+ uint32_t cmd;
+ uint32_t addr;
+ uint32_t data;
} orion_nand_controller_t;
#define CHECK_HALTED \
} \
} while (0)
-int orion_nand_command(struct nand_device_s *device, u8 command)
+static int orion_nand_command(struct nand_device_s *device, uint8_t command)
{
orion_nand_controller_t *hw = device->controller_priv;
target_t *target = hw->target;
return ERROR_OK;
}
-int orion_nand_address(struct nand_device_s *device, u8 address)
+static int orion_nand_address(struct nand_device_s *device, uint8_t address)
{
orion_nand_controller_t *hw = device->controller_priv;
target_t *target = hw->target;
return ERROR_OK;
}
-int orion_nand_read(struct nand_device_s *device, void *data)
+static int orion_nand_read(struct nand_device_s *device, void *data)
{
orion_nand_controller_t *hw = device->controller_priv;
target_t *target = hw->target;
return ERROR_OK;
}
-int orion_nand_write(struct nand_device_s *device, u16 data)
+static int orion_nand_write(struct nand_device_s *device, uint16_t data)
{
orion_nand_controller_t *hw = device->controller_priv;
target_t *target = hw->target;
return ERROR_OK;
}
-int orion_nand_slow_block_write(struct nand_device_s *device, u8 *data, int size)
+static int orion_nand_slow_block_write(struct nand_device_s *device, uint8_t *data, int size)
{
while (size--)
orion_nand_write(device, *data++);
return ERROR_OK;
}
-int orion_nand_fast_block_write(struct nand_device_s *device, u8 *data, int size)
+static int orion_nand_fast_block_write(struct nand_device_s *device, uint8_t *data, int size)
{
orion_nand_controller_t *hw = device->controller_priv;
- target_t *target = hw->target;
- armv4_5_algorithm_t algo;
- reg_param_t reg_params[3];
- u32 target_buf;
int retval;
- static const u32 code[] = {
- 0xe4d13001, /* ldrb r3, [r1], #1 */
- 0xe5c03000, /* strb r3, [r0] */
- 0xe2522001, /* subs r2, r2, #1 */
- 0x1afffffb, /* bne 0 */
- 0xeafffffe, /* b . */
- };
- int code_size = sizeof(code);
-
- if (!hw->copy_area) {
- u8 code_buf[code_size];
- int i;
-
- /* make sure we have a working area */
- if (target_alloc_working_area(target,
- code_size + device->page_size,
- &hw->copy_area) != ERROR_OK)
- {
- return orion_nand_slow_block_write(device, data, size);
- }
-
- /* copy target instructions to target endianness */
- for (i = 0; i < code_size/4; i++)
- target_buffer_set_u32(target, code_buf + i*4, code[i]);
-
- /* write code to working area */
- retval = target->type->write_memory(target,
- hw->copy_area->address,
- 4, code_size/4, code_buf);
- if (retval != ERROR_OK)
- return retval;
- }
+ hw->io.chunk_size = device->page_size;
+
+ retval = arm_nandwrite(&hw->io, data, size);
+ if (retval == ERROR_NAND_NO_BUFFER)
+ retval = orion_nand_slow_block_write(device, data, size);
- /* copy data to target's memory */
- target_buf = hw->copy_area->address + code_size;
- retval = target->type->bulk_write_memory(target, target_buf,
- size/4, data);
- if (retval == ERROR_OK && size & 3) {
- retval = target->type->write_memory(target,
- target_buf + (size & ~3),
- 1, size & 3, data + (size & ~3));
- }
- if (retval != ERROR_OK)
- return retval;
-
- algo.common_magic = ARMV4_5_COMMON_MAGIC;
- algo.core_mode = ARMV4_5_MODE_SVC;
- algo.core_state = ARMV4_5_STATE_ARM;
-
- init_reg_param(®_params[0], "r0", 32, PARAM_IN);
- init_reg_param(®_params[1], "r1", 32, PARAM_IN);
- init_reg_param(®_params[2], "r2", 32, PARAM_IN);
-
- buf_set_u32(reg_params[0].value, 0, 32, hw->data);
- buf_set_u32(reg_params[1].value, 0, 32, target_buf);
- buf_set_u32(reg_params[2].value, 0, 32, size);
-
- retval = target->type->run_algorithm(target, 0, NULL, 3, reg_params,
- hw->copy_area->address,
- hw->copy_area->address + code_size - 4,
- 1000, &algo);
- if (retval != ERROR_OK)
- LOG_ERROR("error executing hosted NAND write");
-
- destroy_reg_param(®_params[0]);
- destroy_reg_param(®_params[1]);
- destroy_reg_param(®_params[2]);
return retval;
}
-int orion_nand_reset(struct nand_device_s *device)
+static int orion_nand_reset(struct nand_device_s *device)
{
return orion_nand_command(device, NAND_CMD_RESET);
}
-int orion_nand_controller_ready(struct nand_device_s *device, int timeout)
+static int orion_nand_controller_ready(struct nand_device_s *device, int timeout)
{
return 1;
}
-int orion_nand_register_commands(struct command_context_s *cmd_ctx)
+static int orion_nand_register_commands(struct command_context_s *cmd_ctx)
{
return ERROR_OK;
}
struct nand_device_s *device)
{
orion_nand_controller_t *hw;
- u32 base;
- u8 ale, cle;
+ uint32_t base;
+ uint8_t ale, cle;
if (argc != 3) {
- LOG_ERROR("arguments must be: <target_number> <NAND_address>\n");
+ LOG_ERROR("arguments must be: <target_id> <NAND_address>\n");
return ERROR_NAND_DEVICE_INVALID;
}
}
device->controller_priv = hw;
- hw->target = get_target_by_num(strtoul(args[1], NULL, 0));
+ hw->target = get_target(args[1]);
if (!hw->target) {
- LOG_ERROR("no target '%s' configured", args[1]);
+ LOG_ERROR("target '%s' not defined", args[1]);
free(hw);
return ERROR_NAND_DEVICE_INVALID;
}
- base = strtoul(args[2], NULL, 0);
+ COMMAND_PARSE_NUMBER(u32, args[2], base);
cle = 0;
ale = 1;
hw->cmd = base + (1 << cle);
hw->addr = base + (1 << ale);
+ hw->io.target = hw->target;
+ hw->io.data = hw->data;
+
return ERROR_OK;
}
-int orion_nand_init(struct nand_device_s *device)
+static int orion_nand_init(struct nand_device_s *device)
{
return ERROR_OK;
}
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