flash/stm32l4x: STM32L5 support programming when TZEN=1 and RDP=0xAA

[fw/openocd] / src / flash / nor / stm32l4x.h

diff --git a/src/flash/nor/stm32l4x.h b/src/flash/nor/stm32l4x.h
index abd8010fc7fe6aa6f5f62a62e69b22568fdab4a4..ebc6ed95aa986ec48fedc8b644eb6243fbac1770 100644 (file)
--- a/src/flash/nor/stm32l4x.h
+++ b/src/flash/nor/stm32l4x.h
@@ -19,18 +19,6 @@
 #ifndef OPENOCD_FLASH_NOR_STM32L4X
 #define OPENOCD_FLASH_NOR_STM32L4X
 
-/* Flash registers offsets */
-#define STM32_FLASH_ACR                        0x00
-#define STM32_FLASH_KEYR               0x08
-#define STM32_FLASH_OPTKEYR            0x0c
-#define STM32_FLASH_SR                 0x10
-#define STM32_FLASH_CR                 0x14
-#define STM32_FLASH_OPTR               0x20
-#define STM32_FLASH_WRP1AR             0x2c
-#define STM32_FLASH_WRP1BR             0x30
-#define STM32_FLASH_WRP2AR             0x4c
-#define STM32_FLASH_WRP2BR             0x50
-
 /* FLASH_CR register bits */
 #define FLASH_PG                               (1 << 0)
 #define FLASH_PER                              (1 << 1)
@@ -68,9 +56,16 @@
 #define OPTKEY1                                        0x08192A3B
 #define OPTKEY2                                        0x4C5D6E7F
 
-#define RDP_LEVEL_0                            0xAA
-#define RDP_LEVEL_1                            0xBB
-#define RDP_LEVEL_2                            0xCC
+/* FLASH_OPTR register bits */
+#define FLASH_RDP_MASK                 0xFF
+#define FLASH_TZEN                             (1 << 31)
+
+/* FLASH secure block based bank 1/2 register offsets */
+#define FLASH_SECBB1(X) (0x80 + 4 * (X - 1))
+#define FLASH_SECBB2(X) (0xA0 + 4 * (X - 1))
+
+#define FLASH_SECBB_SECURE      0xFFFFFFFF
+#define FLASH_SECBB_NON_SECURE  0
 
 /* other registers */
 #define DBGMCU_IDCODE_G0               0x40015800
@@ -78,5 +73,6 @@
 #define DBGMCU_IDCODE_L5               0xE0044000
 
 #define STM32_FLASH_BANK_BASE  0x08000000
+#define STM32_FLASH_S_BANK_BASE        0x0C000000
 
 #endif