flash/stm32l4x: add support of STM32WL5x dual core

[fw/openocd] / src / flash / nor / stm32l4x.h

diff --git a/src/flash/nor/stm32l4x.h b/src/flash/nor/stm32l4x.h
index ba809ff407eaa943370eea718c4fff0e5d2be0ec..7b9162b08606f8658476f022058bd65515b31abd 100644 (file)
--- a/src/flash/nor/stm32l4x.h
+++ b/src/flash/nor/stm32l4x.h
@@ -19,34 +19,44 @@
 #ifndef OPENOCD_FLASH_NOR_STM32L4X
 #define OPENOCD_FLASH_NOR_STM32L4X
 
+/* IMPORTANT: this file is included by stm32l4x driver and flashloader,
+ * so please when changing this file, do not forget to check the flashloader */
+
+/* FIXME: #include "helper/bits.h" cause build errors when compiling
+ * the flashloader, for now just redefine the needed 'BIT 'macro */
+
+#ifndef BIT
+#define BIT(nr)                 (1UL << (nr))
+#endif
+
 /* FLASH_CR register bits */
-#define FLASH_PG                               (1 << 0)
-#define FLASH_PER                              (1 << 1)
-#define FLASH_MER1                             (1 << 2)
+#define FLASH_PG                               BIT(0)
+#define FLASH_PER                              BIT(1)
+#define FLASH_MER1                             BIT(2)
 #define FLASH_PAGE_SHIFT               3
-#define FLASH_BKER                             (1 << 11)
-#define FLASH_BKER_G0                  (1 << 13)
-#define FLASH_MER2                             (1 << 15)
-#define FLASH_STRT                             (1 << 16)
-#define FLASH_OPTSTRT                  (1 << 17)
-#define FLASH_EOPIE                            (1 << 24)
-#define FLASH_ERRIE                            (1 << 25)
-#define FLASH_OBL_LAUNCH               (1 << 27)
-#define FLASH_OPTLOCK                  (1 << 30)
-#define FLASH_LOCK                             (1 << 31)
+#define FLASH_BKER                             BIT(11)
+#define FLASH_BKER_G0                  BIT(13)
+#define FLASH_MER2                             BIT(15)
+#define FLASH_STRT                             BIT(16)
+#define FLASH_OPTSTRT                  BIT(17)
+#define FLASH_EOPIE                            BIT(24)
+#define FLASH_ERRIE                            BIT(25)
+#define FLASH_OBL_LAUNCH               BIT(27)
+#define FLASH_OPTLOCK                  BIT(30)
+#define FLASH_LOCK                             BIT(31)
 
 /* FLASH_SR register bits */
-#define FLASH_BSY                              (1 << 16)
-#define FLASH_BSY2                             (1 << 17)
+#define FLASH_BSY                              BIT(16)
+#define FLASH_BSY2                             BIT(17)
 
 /* Fast programming not used => related errors not used*/
-#define FLASH_PGSERR                   (1 << 7) /* Programming sequence error */
-#define FLASH_SIZERR                   (1 << 6) /* Size error */
-#define FLASH_PGAERR                   (1 << 5) /* Programming alignment error */
-#define FLASH_WRPERR                   (1 << 4) /* Write protection error */
-#define FLASH_PROGERR                  (1 << 3) /* Programming error */
-#define FLASH_OPERR                            (1 << 1) /* Operation error */
-#define FLASH_EOP                              (1 << 0) /* End of operation */
+#define FLASH_PGSERR                   BIT(7) /* Programming sequence error */
+#define FLASH_SIZERR                   BIT(6) /* Size error */
+#define FLASH_PGAERR                   BIT(5) /* Programming alignment error */
+#define FLASH_WRPERR                   BIT(4) /* Write protection error */
+#define FLASH_PROGERR                  BIT(3) /* Programming error */
+#define FLASH_OPERR                            BIT(1) /* Operation error */
+#define FLASH_EOP                              BIT(0) /* End of operation */
 #define FLASH_ERROR                            (FLASH_PGSERR | FLASH_SIZERR | FLASH_PGAERR | \
                                                                FLASH_WRPERR | FLASH_PROGERR | FLASH_OPERR)
 
@@ -60,7 +70,7 @@
 
 /* FLASH_OPTR register bits */
 #define FLASH_RDP_MASK                 0xFF
-#define FLASH_TZEN                             (1 << 31)
+#define FLASH_TZEN                             BIT(31)
 
 /* FLASH secure block based bank 1/2 register offsets */
 #define FLASH_SECBB1(X) (0x80 + 4 * (X - 1))
@@ -73,6 +83,9 @@
 #define DBGMCU_IDCODE_G0               0x40015800
 #define DBGMCU_IDCODE_L4_G4            0xE0042000
 #define DBGMCU_IDCODE_L5               0xE0044000
+#define UID64_DEVNUM                   0x1FFF7580
+#define UID64_IDS                              0x1FFF7584
+#define UID64_IDS_STM32WL              0x0080E115
 
 #define STM32_FLASH_BANK_BASE  0x08000000
 #define STM32_FLASH_S_BANK_BASE        0x0C000000