#include <target/algorithm.h>
#include <target/armv7m.h>
#include "bits.h"
+#include "stm32l4x.h"
/* STM32L4xxx series for reference.
*
*
*/
+/* STM32WBxxx series for reference.
+ *
+ * RM0434 (STM32WB55)
+ * http://www.st.com/resource/en/reference_manual/dm00318631.pdf
+ *
+ * RM0471 (STM32WB50)
+ * http://www.st.com/resource/en/reference_manual/dm00622834.pdf
+ */
+
+/* STM32WLxxx series for reference.
+ *
+ * RM0461 (STM32WLEx)
+ * http://www.st.com/resource/en/reference_manual/dm00530369.pdf
+ */
+
+/* STM32G0xxx series for reference.
+ *
+ * RM0444 (STM32G0x1)
+ * http://www.st.com/resource/en/reference_manual/dm00371828.pdf
+ *
+ * RM0454 (STM32G0x0)
+ * http://www.st.com/resource/en/reference_manual/dm00463896.pdf
+ */
+
+/* STM32G4xxx series for reference.
+ *
+ * RM0440 (STM32G43x/44x/47x/48x/49x/4Ax)
+ * http://www.st.com/resource/en/reference_manual/dm00355726.pdf
+ *
+ * Cat. 2 devices have single bank only, page size is 2kByte.
+ *
+ * Cat. 3 devices have single and dual bank operating modes,
+ * Page size is 2kByte (dual mode) or 4kByte (single mode).
+ *
+ * Bank mode is controlled by bit 22 (DBANK) in option bytes register.
+ * Both banks are treated as a single OpenOCD bank.
+ *
+ * Cat. 4 devices have single bank only, page size is 2kByte.
+ */
+
+/* STM32L5xxx series for reference.
+ *
+ * RM0428 (STM32L552xx/STM32L562xx)
+ * http://www.st.com/resource/en/reference_manual/dm00346336.pdf
+ */
+
/* Erase time can be as high as 25ms, 10x this and assume it's toast... */
#define FLASH_ERASE_TIMEOUT 250
-/* Flash registers offsets */
-#define STM32_FLASH_ACR 0x00
-#define STM32_FLASH_KEYR 0x08
-#define STM32_FLASH_OPTKEYR 0x0c
-#define STM32_FLASH_SR 0x10
-#define STM32_FLASH_CR 0x14
-#define STM32_FLASH_OPTR 0x20
-#define STM32_FLASH_WRP1AR 0x2c
-#define STM32_FLASH_WRP1BR 0x30
-#define STM32_FLASH_WRP2AR 0x4c
-#define STM32_FLASH_WRP2BR 0x50
-
-/* FLASH_CR register bits */
-#define FLASH_PG (1 << 0)
-#define FLASH_PER (1 << 1)
-#define FLASH_MER1 (1 << 2)
-#define FLASH_PAGE_SHIFT 3
-#define FLASH_CR_BKER (1 << 11)
-#define FLASH_MER2 (1 << 15)
-#define FLASH_STRT (1 << 16)
-#define FLASH_OPTSTRT (1 << 17)
-#define FLASH_EOPIE (1 << 24)
-#define FLASH_ERRIE (1 << 25)
-#define FLASH_OBLLAUNCH (1 << 27)
-#define FLASH_OPTLOCK (1 << 30)
-#define FLASH_LOCK (1 << 31)
-
-/* FLASH_SR register bits */
-#define FLASH_BSY (1 << 16)
-/* Fast programming not used => related errors not used*/
-#define FLASH_PGSERR (1 << 7) /* Programming sequence error */
-#define FLASH_SIZERR (1 << 6) /* Size error */
-#define FLASH_PGAERR (1 << 5) /* Programming alignment error */
-#define FLASH_WRPERR (1 << 4) /* Write protection error */
-#define FLASH_PROGERR (1 << 3) /* Programming error */
-#define FLASH_OPERR (1 << 1) /* Operation error */
-#define FLASH_EOP (1 << 0) /* End of operation */
-#define FLASH_ERROR (FLASH_PGSERR | FLASH_SIZERR | FLASH_PGAERR | FLASH_WRPERR | FLASH_PROGERR | FLASH_OPERR)
-
-/* register unlock keys */
-#define KEY1 0x45670123
-#define KEY2 0xCDEF89AB
-
-/* option register unlock key */
-#define OPTKEY1 0x08192A3B
-#define OPTKEY2 0x4C5D6E7F
-
-#define RDP_LEVEL_0 0xAA
-#define RDP_LEVEL_1 0xBB
-#define RDP_LEVEL_2 0xCC
-
-
-/* other registers */
-#define DBGMCU_IDCODE 0xE0042000
+enum stm32l4_flash_reg_index {
+ STM32_FLASH_ACR_INDEX,
+ STM32_FLASH_KEYR_INDEX,
+ STM32_FLASH_OPTKEYR_INDEX,
+ STM32_FLASH_SR_INDEX,
+ STM32_FLASH_CR_INDEX,
+ STM32_FLASH_OPTR_INDEX,
+ STM32_FLASH_WRP1AR_INDEX,
+ STM32_FLASH_WRP1BR_INDEX,
+ STM32_FLASH_WRP2AR_INDEX,
+ STM32_FLASH_WRP2BR_INDEX,
+ STM32_FLASH_REG_INDEX_NUM,
+};
+
+static const uint32_t stm32l4_flash_regs[STM32_FLASH_REG_INDEX_NUM] = {
+ [STM32_FLASH_ACR_INDEX] = 0x000,
+ [STM32_FLASH_KEYR_INDEX] = 0x008,
+ [STM32_FLASH_OPTKEYR_INDEX] = 0x00C,
+ [STM32_FLASH_SR_INDEX] = 0x010,
+ [STM32_FLASH_CR_INDEX] = 0x014,
+ [STM32_FLASH_OPTR_INDEX] = 0x020,
+ [STM32_FLASH_WRP1AR_INDEX] = 0x02C,
+ [STM32_FLASH_WRP1BR_INDEX] = 0x030,
+ [STM32_FLASH_WRP2AR_INDEX] = 0x04C,
+ [STM32_FLASH_WRP2BR_INDEX] = 0x050,
+};
+static const uint32_t stm32l5_ns_flash_regs[STM32_FLASH_REG_INDEX_NUM] = {
+ [STM32_FLASH_ACR_INDEX] = 0x000,
+ [STM32_FLASH_KEYR_INDEX] = 0x008,
+ [STM32_FLASH_OPTKEYR_INDEX] = 0x010,
+ [STM32_FLASH_SR_INDEX] = 0x020,
+ [STM32_FLASH_CR_INDEX] = 0x028,
+ [STM32_FLASH_OPTR_INDEX] = 0x040,
+ [STM32_FLASH_WRP1AR_INDEX] = 0x058,
+ [STM32_FLASH_WRP1BR_INDEX] = 0x05C,
+ [STM32_FLASH_WRP2AR_INDEX] = 0x068,
+ [STM32_FLASH_WRP2BR_INDEX] = 0x06C,
+};
struct stm32l4_rev {
const uint16_t rev;
const uint16_t max_flash_size_kb;
const bool has_dual_bank;
const uint32_t flash_regs_base;
+ const uint32_t *default_flash_regs;
const uint32_t fsize_addr;
};
struct stm32l4_flash_bank {
- int probed;
+ bool probed;
uint32_t idcode;
- int bank1_sectors;
+ unsigned int bank1_sectors;
bool dual_bank_mode;
int hole_sectors;
+ uint32_t user_bank_size;
+ uint32_t wrpxxr_mask;
const struct stm32l4_part_info *part_info;
+ const uint32_t *flash_regs;
};
+/* human readable list of families this drivers supports (sorted alphabetically) */
+static const char *device_families = "STM32G0/G4/L4/L4+/L5/WB/WL";
+
static const struct stm32l4_rev stm32_415_revs[] = {
{ 0x1000, "1" }, { 0x1001, "2" }, { 0x1003, "3" }, { 0x1007, "4" }
};
{ 0x1000, "A" }, { 0x1001, "Z" }, { 0x2001, "Y" },
};
+static const struct stm32l4_rev stm32_460_revs[] = {
+ { 0x1000, "A/Z" } /* A and Z, no typo in RM! */, { 0x2000, "B" },
+};
+
static const struct stm32l4_rev stm32_461_revs[] = {
{ 0x1000, "A" }, { 0x2000, "B" },
};
static const struct stm32l4_rev stm32_462_revs[] = {
- { 0x1000, "A" }, { 0x1001, "Z" }, { 0x2001, "Y" },
+ { 0x1000, "A" }, { 0x1001, "Z" }, { 0x2001, "Y" },
};
static const struct stm32l4_rev stm32_464_revs[] = {
- { 0x1000, "A" },
+ { 0x1000, "A" }, { 0x1001, "Z" }, { 0x2001, "Y" },
+};
+
+static const struct stm32l4_rev stm32_466_revs[] = {
+ { 0x1000, "A" }, { 0x1001, "Z" }, { 0x2000, "B" },
+};
+
+static const struct stm32l4_rev stm32_468_revs[] = {
+ { 0x1000, "A" }, { 0x2000, "B" }, { 0x2001, "Z" },
+};
+
+static const struct stm32l4_rev stm32_469_revs[] = {
+ { 0x1000, "A" }, { 0x2000, "B" }, { 0x2001, "Z" },
};
static const struct stm32l4_rev stm32_470_revs[] = {
};
static const struct stm32l4_rev stm32_471_revs[] = {
- { 0x1000, "1" },
+ { 0x1001, "Z" },
+};
+
+static const struct stm32l4_rev stm32_472_revs[] = {
+ { 0x1000, "A" }, { 0x2000, "B" },
+};
+
+static const struct stm32l4_rev stm32_479_revs[] = {
+ { 0x1000, "A" },
};
static const struct stm32l4_rev stm32_495_revs[] = {
{ 0x2001, "2.1" },
};
+static const struct stm32l4_rev stm32_496_revs[] = {
+ { 0x1000, "A" },
+};
+
+static const struct stm32l4_rev stm32_497_revs[] = {
+ { 0x1000, "1.0" },
+};
+
static const struct stm32l4_part_info stm32l4_parts[] = {
{
.id = 0x415,
.max_flash_size_kb = 1024,
.has_dual_bank = true,
.flash_regs_base = 0x40022000,
+ .default_flash_regs = stm32l4_flash_regs,
.fsize_addr = 0x1FFF75E0,
},
{
.max_flash_size_kb = 256,
.has_dual_bank = false,
.flash_regs_base = 0x40022000,
+ .default_flash_regs = stm32l4_flash_regs,
+ .fsize_addr = 0x1FFF75E0,
+ },
+ {
+ .id = 0x460,
+ .revs = stm32_460_revs,
+ .num_revs = ARRAY_SIZE(stm32_460_revs),
+ .device_str = "STM32G07/G08xx",
+ .max_flash_size_kb = 128,
+ .has_dual_bank = false,
+ .flash_regs_base = 0x40022000,
+ .default_flash_regs = stm32l4_flash_regs,
.fsize_addr = 0x1FFF75E0,
},
{
.max_flash_size_kb = 1024,
.has_dual_bank = true,
.flash_regs_base = 0x40022000,
+ .default_flash_regs = stm32l4_flash_regs,
.fsize_addr = 0x1FFF75E0,
},
{
.max_flash_size_kb = 512,
.has_dual_bank = false,
.flash_regs_base = 0x40022000,
+ .default_flash_regs = stm32l4_flash_regs,
.fsize_addr = 0x1FFF75E0,
},
{
.max_flash_size_kb = 128,
.has_dual_bank = false,
.flash_regs_base = 0x40022000,
+ .default_flash_regs = stm32l4_flash_regs,
+ .fsize_addr = 0x1FFF75E0,
+ },
+ {
+ .id = 0x466,
+ .revs = stm32_466_revs,
+ .num_revs = ARRAY_SIZE(stm32_466_revs),
+ .device_str = "STM32G03/G04xx",
+ .max_flash_size_kb = 64,
+ .has_dual_bank = false,
+ .flash_regs_base = 0x40022000,
+ .default_flash_regs = stm32l4_flash_regs,
+ .fsize_addr = 0x1FFF75E0,
+ },
+ {
+ .id = 0x468,
+ .revs = stm32_468_revs,
+ .num_revs = ARRAY_SIZE(stm32_468_revs),
+ .device_str = "STM32G43/G44xx",
+ .max_flash_size_kb = 128,
+ .has_dual_bank = false,
+ .flash_regs_base = 0x40022000,
+ .default_flash_regs = stm32l4_flash_regs,
+ .fsize_addr = 0x1FFF75E0,
+ },
+ {
+ .id = 0x469,
+ .revs = stm32_469_revs,
+ .num_revs = ARRAY_SIZE(stm32_469_revs),
+ .device_str = "STM32G47/G48xx",
+ .max_flash_size_kb = 512,
+ .has_dual_bank = true,
+ .flash_regs_base = 0x40022000,
+ .default_flash_regs = stm32l4_flash_regs,
.fsize_addr = 0x1FFF75E0,
},
{
.max_flash_size_kb = 2048,
.has_dual_bank = true,
.flash_regs_base = 0x40022000,
+ .default_flash_regs = stm32l4_flash_regs,
.fsize_addr = 0x1FFF75E0,
},
{
.max_flash_size_kb = 1024,
.has_dual_bank = true,
.flash_regs_base = 0x40022000,
+ .default_flash_regs = stm32l4_flash_regs,
+ .fsize_addr = 0x1FFF75E0,
+ },
+ {
+ .id = 0x472,
+ .revs = stm32_472_revs,
+ .num_revs = ARRAY_SIZE(stm32_472_revs),
+ .device_str = "STM32L55/L56xx",
+ .max_flash_size_kb = 512,
+ .has_dual_bank = true,
+ .flash_regs_base = 0x40022000,
+ .default_flash_regs = stm32l5_ns_flash_regs,
+ .fsize_addr = 0x0BFA05E0,
+ },
+ {
+ .id = 0x479,
+ .revs = stm32_479_revs,
+ .num_revs = ARRAY_SIZE(stm32_479_revs),
+ .device_str = "STM32G49/G4Axx",
+ .max_flash_size_kb = 512,
+ .has_dual_bank = false,
+ .flash_regs_base = 0x40022000,
+ .default_flash_regs = stm32l4_flash_regs,
.fsize_addr = 0x1FFF75E0,
},
{
.max_flash_size_kb = 1024,
.has_dual_bank = false,
.flash_regs_base = 0x58004000,
+ .default_flash_regs = stm32l4_flash_regs,
+ .fsize_addr = 0x1FFF75E0,
+ },
+ {
+ .id = 0x496,
+ .revs = stm32_496_revs,
+ .num_revs = ARRAY_SIZE(stm32_496_revs),
+ .device_str = "STM32WB3x",
+ .max_flash_size_kb = 512,
+ .has_dual_bank = false,
+ .flash_regs_base = 0x58004000,
+ .default_flash_regs = stm32l4_flash_regs,
+ .fsize_addr = 0x1FFF75E0,
+ },
+ {
+ .id = 0x497,
+ .revs = stm32_497_revs,
+ .num_revs = ARRAY_SIZE(stm32_497_revs),
+ .device_str = "STM32WLEx",
+ .max_flash_size_kb = 256,
+ .has_dual_bank = false,
+ .flash_regs_base = 0x58004000,
+ .default_flash_regs = stm32l4_flash_regs,
.fsize_addr = 0x1FFF75E0,
},
};
if (CMD_ARGC < 6)
return ERROR_COMMAND_SYNTAX_ERROR;
- stm32l4_info = malloc(sizeof(struct stm32l4_flash_bank));
+ stm32l4_info = calloc(1, sizeof(struct stm32l4_flash_bank));
if (!stm32l4_info)
return ERROR_FAIL; /* Checkme: What better error to use?*/
bank->driver_priv = stm32l4_info;
* Ask the flash infrastructure to ensure required alignment */
bank->write_start_alignment = bank->write_end_alignment = 8;
- stm32l4_info->probed = 0;
+ stm32l4_info->probed = false;
+ stm32l4_info->user_bank_size = bank->size;
return ERROR_OK;
}
return stm32l4_info->part_info->flash_regs_base + reg_offset;
}
+static inline uint32_t stm32l4_get_flash_reg_by_index(struct flash_bank *bank,
+ enum stm32l4_flash_reg_index reg_index)
+{
+ struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
+ return stm32l4_get_flash_reg(bank, stm32l4_info->flash_regs[reg_index]);
+}
+
static inline int stm32l4_read_flash_reg(struct flash_bank *bank, uint32_t reg_offset, uint32_t *value)
{
return target_read_u32(bank->target, stm32l4_get_flash_reg(bank, reg_offset), value);
}
+static inline int stm32l4_read_flash_reg_by_index(struct flash_bank *bank,
+ enum stm32l4_flash_reg_index reg_index, uint32_t *value)
+{
+ struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
+ return stm32l4_read_flash_reg(bank, stm32l4_info->flash_regs[reg_index], value);
+}
+
static inline int stm32l4_write_flash_reg(struct flash_bank *bank, uint32_t reg_offset, uint32_t value)
{
return target_write_u32(bank->target, stm32l4_get_flash_reg(bank, reg_offset), value);
}
+static inline int stm32l4_write_flash_reg_by_index(struct flash_bank *bank,
+ enum stm32l4_flash_reg_index reg_index, uint32_t value)
+{
+ struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
+ return stm32l4_write_flash_reg(bank, stm32l4_info->flash_regs[reg_index], value);
+}
+
static int stm32l4_wait_status_busy(struct flash_bank *bank, int timeout)
{
uint32_t status;
/* wait for busy to clear */
for (;;) {
- retval = stm32l4_read_flash_reg(bank, STM32_FLASH_SR, &status);
+ retval = stm32l4_read_flash_reg_by_index(bank, STM32_FLASH_SR_INDEX, &status);
if (retval != ERROR_OK)
return retval;
LOG_DEBUG("status: 0x%" PRIx32 "", status);
alive_sleep(1);
}
-
if (status & FLASH_WRPERR) {
LOG_ERROR("stm32x device protected");
retval = ERROR_FAIL;
/* If this operation fails, we ignore it and report the original
* retval
*/
- stm32l4_write_flash_reg(bank, STM32_FLASH_SR, status & FLASH_ERROR);
+ stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_SR_INDEX, status & FLASH_ERROR);
}
return retval;
/* first check if not already unlocked
* otherwise writing on STM32_FLASH_KEYR will fail
*/
- int retval = stm32l4_read_flash_reg(bank, STM32_FLASH_CR, &ctrl);
+ int retval = stm32l4_read_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, &ctrl);
if (retval != ERROR_OK)
return retval;
return ERROR_OK;
/* unlock flash registers */
- retval = stm32l4_write_flash_reg(bank, STM32_FLASH_KEYR, KEY1);
+ retval = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_KEYR_INDEX, KEY1);
if (retval != ERROR_OK)
return retval;
- retval = stm32l4_write_flash_reg(bank, STM32_FLASH_KEYR, KEY2);
+ retval = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_KEYR_INDEX, KEY2);
if (retval != ERROR_OK)
return retval;
- retval = stm32l4_read_flash_reg(bank, STM32_FLASH_CR, &ctrl);
+ retval = stm32l4_read_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, &ctrl);
if (retval != ERROR_OK)
return retval;
{
uint32_t ctrl;
- int retval = stm32l4_read_flash_reg(bank, STM32_FLASH_CR, &ctrl);
+ int retval = stm32l4_read_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, &ctrl);
if (retval != ERROR_OK)
return retval;
return ERROR_OK;
/* unlock option registers */
- retval = stm32l4_write_flash_reg(bank, STM32_FLASH_OPTKEYR, OPTKEY1);
+ retval = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_OPTKEYR_INDEX, OPTKEY1);
if (retval != ERROR_OK)
return retval;
- retval = stm32l4_write_flash_reg(bank, STM32_FLASH_OPTKEYR, OPTKEY2);
+ retval = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_OPTKEYR_INDEX, OPTKEY2);
if (retval != ERROR_OK)
return retval;
- retval = stm32l4_read_flash_reg(bank, STM32_FLASH_CR, &ctrl);
+ retval = stm32l4_read_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, &ctrl);
if (retval != ERROR_OK)
return retval;
return ERROR_OK;
}
-static int stm32l4_write_option(struct flash_bank *bank, uint32_t reg_offset, uint32_t value, uint32_t mask)
+static int stm32l4_write_option(struct flash_bank *bank, uint32_t reg_offset,
+ uint32_t value, uint32_t mask)
{
uint32_t optiondata;
+ int retval, retval2;
- int retval = stm32l4_read_flash_reg(bank, reg_offset, &optiondata);
+ retval = stm32l4_read_flash_reg(bank, reg_offset, &optiondata);
if (retval != ERROR_OK)
return retval;
retval = stm32l4_unlock_reg(bank);
if (retval != ERROR_OK)
- return retval;
+ goto err_lock;
retval = stm32l4_unlock_option_reg(bank);
if (retval != ERROR_OK)
- return retval;
+ goto err_lock;
optiondata = (optiondata & ~mask) | (value & mask);
retval = stm32l4_write_flash_reg(bank, reg_offset, optiondata);
if (retval != ERROR_OK)
- return retval;
+ goto err_lock;
- retval = stm32l4_write_flash_reg(bank, STM32_FLASH_CR, FLASH_OPTSTRT);
+ retval = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, FLASH_OPTSTRT);
if (retval != ERROR_OK)
- return retval;
+ goto err_lock;
retval = stm32l4_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
+
+err_lock:
+ retval2 = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, FLASH_LOCK | FLASH_OPTLOCK);
+
if (retval != ERROR_OK)
return retval;
- return retval;
+ return retval2;
}
static int stm32l4_protect_check(struct flash_bank *bank)
struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
uint32_t wrp1ar, wrp1br, wrp2ar, wrp2br;
- stm32l4_read_flash_reg(bank, STM32_FLASH_WRP1AR, &wrp1ar);
- stm32l4_read_flash_reg(bank, STM32_FLASH_WRP1BR, &wrp1br);
- stm32l4_read_flash_reg(bank, STM32_FLASH_WRP2AR, &wrp2ar);
- stm32l4_read_flash_reg(bank, STM32_FLASH_WRP2BR, &wrp2br);
-
- const uint8_t wrp1a_start = wrp1ar & 0xFF;
- const uint8_t wrp1a_end = (wrp1ar >> 16) & 0xFF;
- const uint8_t wrp1b_start = wrp1br & 0xFF;
- const uint8_t wrp1b_end = (wrp1br >> 16) & 0xFF;
- const uint8_t wrp2a_start = wrp2ar & 0xFF;
- const uint8_t wrp2a_end = (wrp2ar >> 16) & 0xFF;
- const uint8_t wrp2b_start = wrp2br & 0xFF;
- const uint8_t wrp2b_end = (wrp2br >> 16) & 0xFF;
-
- for (int i = 0; i < bank->num_sectors; i++) {
+ stm32l4_read_flash_reg_by_index(bank, STM32_FLASH_WRP1AR_INDEX, &wrp1ar);
+ stm32l4_read_flash_reg_by_index(bank, STM32_FLASH_WRP1BR_INDEX, &wrp1br);
+ if (stm32l4_info->part_info->has_dual_bank) {
+ stm32l4_read_flash_reg_by_index(bank, STM32_FLASH_WRP2AR_INDEX, &wrp2ar);
+ stm32l4_read_flash_reg_by_index(bank, STM32_FLASH_WRP2BR_INDEX, &wrp2br);
+ } else {
+ /* prevent uninitialized errors */
+ wrp2ar = 0;
+ wrp2br = 0;
+ }
+
+ const uint8_t wrp1a_start = wrp1ar & stm32l4_info->wrpxxr_mask;
+ const uint8_t wrp1a_end = (wrp1ar >> 16) & stm32l4_info->wrpxxr_mask;
+ const uint8_t wrp1b_start = wrp1br & stm32l4_info->wrpxxr_mask;
+ const uint8_t wrp1b_end = (wrp1br >> 16) & stm32l4_info->wrpxxr_mask;
+ const uint8_t wrp2a_start = wrp2ar & stm32l4_info->wrpxxr_mask;
+ const uint8_t wrp2a_end = (wrp2ar >> 16) & stm32l4_info->wrpxxr_mask;
+ const uint8_t wrp2b_start = wrp2br & stm32l4_info->wrpxxr_mask;
+ const uint8_t wrp2b_end = (wrp2br >> 16) & stm32l4_info->wrpxxr_mask;
+
+ for (unsigned int i = 0; i < bank->num_sectors; i++) {
if (i < stm32l4_info->bank1_sectors) {
if (((i >= wrp1a_start) &&
(i <= wrp1a_end)) ||
else
bank->sectors[i].is_protected = 0;
} else {
+ assert(stm32l4_info->part_info->has_dual_bank == true);
uint8_t snb;
snb = i - stm32l4_info->bank1_sectors;
if (((snb >= wrp2a_start) &&
return ERROR_OK;
}
-static int stm32l4_erase(struct flash_bank *bank, int first, int last)
+static int stm32l4_erase(struct flash_bank *bank, unsigned int first,
+ unsigned int last)
{
struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
- int i;
- int retval;
+ int retval, retval2;
- assert(first < bank->num_sectors);
- assert(last < bank->num_sectors);
+ assert((first <= last) && (last < bank->num_sectors));
if (bank->target->state != TARGET_HALTED) {
LOG_ERROR("Target not halted");
retval = stm32l4_unlock_reg(bank);
if (retval != ERROR_OK)
- return retval;
+ goto err_lock;
/*
Sector Erase
To erase a sector, follow the procedure below:
1. Check that no Flash memory operation is ongoing by
- checking the BSY bit in the FLASH_SR register
+ checking the BSY bit in the FLASH_SR register
2. Set the PER bit and select the page and bank
you wish to erase in the FLASH_CR register
3. Set the STRT bit in the FLASH_CR register
4. Wait for the BSY bit to be cleared
*/
- for (i = first; i <= last; i++) {
+ for (unsigned int i = first; i <= last; i++) {
uint32_t erase_flags;
erase_flags = FLASH_PER | FLASH_STRT;
erase_flags |= snb << FLASH_PAGE_SHIFT | FLASH_CR_BKER;
} else
erase_flags |= i << FLASH_PAGE_SHIFT;
- retval = stm32l4_write_flash_reg(bank, STM32_FLASH_CR, erase_flags);
+ retval = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, erase_flags);
if (retval != ERROR_OK)
- return retval;
+ break;
retval = stm32l4_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
if (retval != ERROR_OK)
- return retval;
+ break;
bank->sectors[i].is_erased = 1;
}
- retval = stm32l4_write_flash_reg(bank, STM32_FLASH_CR, FLASH_LOCK);
+err_lock:
+ retval2 = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, FLASH_LOCK);
+
if (retval != ERROR_OK)
return retval;
- return ERROR_OK;
+ return retval2;
}
-static int stm32l4_protect(struct flash_bank *bank, int set, int first, int last)
+static int stm32l4_protect(struct flash_bank *bank, int set, unsigned int first,
+ unsigned int last)
{
struct target *target = bank->target;
struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
reg_value = ((last & 0xFF) << 16) | begin;
}
- ret = stm32l4_write_option(bank, STM32_FLASH_WRP2AR, reg_value, 0xffffffff);
+ ret = stm32l4_write_option(bank, stm32l4_info->flash_regs[STM32_FLASH_WRP2AR_INDEX], reg_value, 0xffffffff);
}
/* Bank 1 */
reg_value = 0xFF; /* Default to bank un-protected */
reg_value = (end << 16) | (first & 0xFF);
}
- ret = stm32l4_write_option(bank, STM32_FLASH_WRP1AR, reg_value, 0xffffffff);
+ ret = stm32l4_write_option(bank, stm32l4_info->flash_regs[STM32_FLASH_WRP1AR_INDEX], reg_value, 0xffffffff);
}
return ret;
/* Count is in double-words */
static int stm32l4_write_block(struct flash_bank *bank, const uint8_t *buffer,
- uint32_t offset, uint32_t count)
+ uint32_t offset, uint32_t count)
{
struct target *target = bank->target;
- struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
- uint32_t buffer_size = 16384;
+ uint32_t buffer_size;
struct working_area *write_algorithm;
struct working_area *source;
uint32_t address = bank->base + offset;
- struct reg_param reg_params[5];
+ struct reg_param reg_params[6];
struct armv7m_algorithm armv7m_info;
int retval = ERROR_OK;
return retval;
}
- /* memory buffer */
- while (target_alloc_working_area_try(target, buffer_size, &source) !=
- ERROR_OK) {
- buffer_size /= 2;
- if (buffer_size <= 256) {
- /* we already allocated the writing code, but failed to get a
- * buffer, free the algorithm */
- target_free_working_area(target, write_algorithm);
-
- LOG_WARNING("large enough working area not available, can't do block memory writes");
- return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
- }
+ /* memory buffer, size *must* be multiple of dword plus one dword for rp and one for wp */
+ buffer_size = target_get_working_area_avail(target) & ~(2 * sizeof(uint32_t) - 1);
+ if (buffer_size < 256) {
+ LOG_WARNING("large enough working area not available, can't do block memory writes");
+ return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+ } else if (buffer_size > 16384) {
+ /* probably won't benefit from more than 16k ... */
+ buffer_size = 16384;
+ }
+
+ if (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK) {
+ LOG_ERROR("allocating working area failed");
+ return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
init_reg_param(®_params[1], "r1", 32, PARAM_OUT); /* buffer end */
init_reg_param(®_params[2], "r2", 32, PARAM_OUT); /* target address */
init_reg_param(®_params[3], "r3", 32, PARAM_OUT); /* count (double word-64bit) */
- init_reg_param(®_params[4], "r4", 32, PARAM_OUT); /* flash regs base */
+ init_reg_param(®_params[4], "r4", 32, PARAM_OUT); /* flash status register */
+ init_reg_param(®_params[5], "r5", 32, PARAM_OUT); /* flash control register */
buf_set_u32(reg_params[0].value, 0, 32, source->address);
buf_set_u32(reg_params[1].value, 0, 32, source->address + source->size);
buf_set_u32(reg_params[2].value, 0, 32, address);
buf_set_u32(reg_params[3].value, 0, 32, count);
- buf_set_u32(reg_params[4].value, 0, 32, stm32l4_info->part_info->flash_regs_base);
+ buf_set_u32(reg_params[4].value, 0, 32, stm32l4_get_flash_reg_by_index(bank, STM32_FLASH_SR_INDEX));
+ buf_set_u32(reg_params[5].value, 0, 32, stm32l4_get_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX));
retval = target_run_flash_async_algorithm(target, buffer, count, 8,
0, NULL,
- 5, reg_params,
+ ARRAY_SIZE(reg_params), reg_params,
source->address, source->size,
write_algorithm->address, 0,
&armv7m_info);
if (error != 0) {
LOG_ERROR("flash write failed = %08" PRIx32, error);
/* Clear but report errors */
- stm32l4_write_flash_reg(bank, STM32_FLASH_SR, error);
+ stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_SR_INDEX, error);
retval = ERROR_FAIL;
}
}
destroy_reg_param(®_params[2]);
destroy_reg_param(®_params[3]);
destroy_reg_param(®_params[4]);
+ destroy_reg_param(®_params[5]);
return retval;
}
static int stm32l4_write(struct flash_bank *bank, const uint8_t *buffer,
- uint32_t offset, uint32_t count)
+ uint32_t offset, uint32_t count)
{
- int retval, retval2;
+ int retval = ERROR_OK, retval2;
if (bank->target->state != TARGET_HALTED) {
LOG_ERROR("Target not halted");
assert(offset % 8 == 0);
assert(count % 8 == 0);
- retval = stm32l4_unlock_reg(bank);
+ /* STM32G4xxx Cat. 3 devices may have gaps between banks, check whether
+ * data to be written does not go into a gap:
+ * suppose buffer is fully contained in bank from sector 0 to sector
+ * num->sectors - 1 and sectors are ordered according to offset
+ */
+ struct flash_sector *head = &bank->sectors[0];
+ struct flash_sector *tail = &bank->sectors[bank->num_sectors - 1];
+
+ while ((head < tail) && (offset >= (head + 1)->offset)) {
+ /* buffer does not intersect head nor gap behind head */
+ head++;
+ }
+
+ while ((head < tail) && (offset + count <= (tail - 1)->offset + (tail - 1)->size)) {
+ /* buffer does not intersect tail nor gap before tail */
+ --tail;
+ }
+
+ LOG_DEBUG("data: 0x%08" PRIx32 " - 0x%08" PRIx32 ", sectors: 0x%08" PRIx32 " - 0x%08" PRIx32,
+ offset, offset + count - 1, head->offset, tail->offset + tail->size - 1);
+
+ /* Now check that there is no gap from head to tail, this should work
+ * even for multiple or non-symmetric gaps
+ */
+ while (head < tail) {
+ if (head->offset + head->size != (head + 1)->offset) {
+ LOG_ERROR("write into gap from " TARGET_ADDR_FMT " to " TARGET_ADDR_FMT,
+ bank->base + head->offset + head->size,
+ bank->base + (head + 1)->offset - 1);
+ retval = ERROR_FLASH_DST_OUT_OF_BANK;
+ }
+ head++;
+ }
+
if (retval != ERROR_OK)
return retval;
+ retval = stm32l4_unlock_reg(bank);
+ if (retval != ERROR_OK)
+ goto err_lock;
+
retval = stm32l4_write_block(bank, buffer, offset, count / 8);
- retval2 = stm32l4_write_flash_reg(bank, STM32_FLASH_CR, FLASH_LOCK);
+err_lock:
+ retval2 = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, FLASH_LOCK);
if (retval != ERROR_OK) {
LOG_ERROR("block write failed");
static int stm32l4_read_idcode(struct flash_bank *bank, uint32_t *id)
{
- int retval = target_read_u32(bank->target, DBGMCU_IDCODE, id);
- if (retval != ERROR_OK)
- return retval;
+ int retval;
- return retval;
+ /* try reading possible IDCODE registers, in the following order */
+ uint32_t DBGMCU_IDCODE[] = {DBGMCU_IDCODE_L4_G4, DBGMCU_IDCODE_G0, DBGMCU_IDCODE_L5};
+
+ for (unsigned int i = 0; i < ARRAY_SIZE(DBGMCU_IDCODE); i++) {
+ retval = target_read_u32(bank->target, DBGMCU_IDCODE[i], id);
+ if ((retval == ERROR_OK) && ((*id & 0xfff) != 0) && ((*id & 0xfff) != 0xfff))
+ return ERROR_OK;
+ }
+
+ LOG_ERROR("can't get the device id");
+ return (retval == ERROR_OK) ? ERROR_FAIL : retval;
}
static int stm32l4_probe(struct flash_bank *bank)
struct target *target = bank->target;
struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
const struct stm32l4_part_info *part_info;
- int i;
- uint16_t flash_size_in_kb = 0xffff;
+ uint16_t flash_size_kb = 0xffff;
uint32_t device_id;
uint32_t options;
- stm32l4_info->probed = 0;
+ stm32l4_info->probed = false;
- /* read stm32 device id register */
+ /* read stm32 device id registers */
int retval = stm32l4_read_idcode(bank, &stm32l4_info->idcode);
if (retval != ERROR_OK)
return retval;
}
if (!stm32l4_info->part_info) {
- LOG_WARNING("Cannot identify target as an STM32 L4 or WB family device.");
+ LOG_WARNING("Cannot identify target as an %s family device.", device_families);
return ERROR_FAIL;
}
part_info = stm32l4_info->part_info;
+ stm32l4_info->flash_regs = stm32l4_info->part_info->default_flash_regs;
char device_info[1024];
retval = bank->driver->info(bank, device_info, sizeof(device_info));
LOG_INFO("device idcode = 0x%08" PRIx32 " (%s)", stm32l4_info->idcode, device_info);
/* get flash size from target. */
- retval = target_read_u16(target, part_info->fsize_addr, &flash_size_in_kb);
+ retval = target_read_u16(target, part_info->fsize_addr, &flash_size_kb);
/* failed reading flash size or flash size invalid (early silicon),
* default to max target family */
- if (retval != ERROR_OK || flash_size_in_kb == 0xffff || flash_size_in_kb == 0
- || flash_size_in_kb > part_info->max_flash_size_kb) {
+ if (retval != ERROR_OK || flash_size_kb == 0xffff || flash_size_kb == 0
+ || flash_size_kb > part_info->max_flash_size_kb) {
LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming %dk flash",
part_info->max_flash_size_kb);
- flash_size_in_kb = part_info->max_flash_size_kb;
+ flash_size_kb = part_info->max_flash_size_kb;
}
- LOG_INFO("flash size = %dkbytes", flash_size_in_kb);
+ /* if the user sets the size manually then ignore the probed value
+ * this allows us to work around devices that have a invalid flash size register value */
+ if (stm32l4_info->user_bank_size) {
+ LOG_WARNING("overriding size register by configured bank size - MAY CAUSE TROUBLE");
+ flash_size_kb = stm32l4_info->user_bank_size / 1024;
+ }
+
+ LOG_INFO("flash size = %dkbytes", flash_size_kb);
/* did we assign a flash size? */
- assert((flash_size_in_kb != 0xffff) && flash_size_in_kb);
+ assert((flash_size_kb != 0xffff) && flash_size_kb);
/* read flash option register */
- retval = stm32l4_read_flash_reg(bank, STM32_FLASH_OPTR, &options);
+ retval = stm32l4_read_flash_reg_by_index(bank, STM32_FLASH_OPTR_INDEX, &options);
if (retval != ERROR_OK)
return retval;
stm32l4_info->hole_sectors = 0;
int num_pages = 0;
- int page_size = 0;
+ int page_size_kb = 0;
stm32l4_info->dual_bank_mode = false;
+ bool use_dbank_bit = false;
switch (device_id) {
- case 0x415:
- case 0x461:
+ case 0x415: /* STM32L47/L48xx */
+ case 0x461: /* STM32L49/L4Axx */
/* if flash size is max (1M) the device is always dual bank
* 0x415: has variants with 512K
* 0x461: has variants with 512 and 256
* else -> dual bank without gap
* note: the page size is invariant
*/
- page_size = 2048;
- num_pages = flash_size_in_kb / 2;
+ page_size_kb = 2;
+ num_pages = flash_size_kb / page_size_kb;
stm32l4_info->bank1_sectors = num_pages;
/* check DUAL_BANK bit[21] if the flash is less than 1M */
- if (flash_size_in_kb == 1024 || (options & BIT(21))) {
+ if (flash_size_kb == 1024 || (options & BIT(21))) {
stm32l4_info->dual_bank_mode = true;
stm32l4_info->bank1_sectors = num_pages / 2;
}
break;
- case 0x435:
- case 0x462:
- case 0x464:
+ case 0x435: /* STM32L43/L44xx */
+ case 0x460: /* STM32G07/G08xx */
+ case 0x462: /* STM32L45/L46xx */
+ case 0x464: /* STM32L41/L42xx */
+ case 0x466: /* STM32G03/G04xx */
+ case 0x468: /* STM32G43/G44xx */
+ case 0x479: /* STM32G49/G4Axx */
+ case 0x497: /* STM32WLEx */
/* single bank flash */
- page_size = 2048;
- num_pages = flash_size_in_kb / 2;
+ page_size_kb = 2;
+ num_pages = flash_size_kb / page_size_kb;
stm32l4_info->bank1_sectors = num_pages;
break;
- case 0x470:
- case 0x471:
+ case 0x469: /* STM32G47/G48xx */
+ /* STM32G47/8 can be single/dual bank:
+ * if DUAL_BANK = 0 -> single bank
+ * else -> dual bank WITH gap
+ */
+ page_size_kb = 4;
+ num_pages = flash_size_kb / page_size_kb;
+ stm32l4_info->bank1_sectors = num_pages;
+ if (options & BIT(22)) {
+ stm32l4_info->dual_bank_mode = true;
+ page_size_kb = 2;
+ num_pages = flash_size_kb / page_size_kb;
+ stm32l4_info->bank1_sectors = num_pages / 2;
+
+ /* for devices with trimmed flash, there is a gap between both banks */
+ stm32l4_info->hole_sectors =
+ (part_info->max_flash_size_kb - flash_size_kb) / (2 * page_size_kb);
+ }
+ break;
+ case 0x470: /* STM32L4R/L4Sxx */
+ case 0x471: /* STM32L4P5/L4Q5x */
/* STM32L4R/S can be single/dual bank:
* if size = 2M check DBANK bit(22)
* if size = 1M check DB1M bit(21)
* STM32L4P/Q can be single/dual bank
* if size = 1M check DBANK bit(22)
* if size = 512K check DB512K bit(21)
- * in single bank configuration the page size is 8K
- * else (dual bank) the page size is 4K without gap between banks
*/
- page_size = 8192;
- num_pages = flash_size_in_kb / 8;
+ page_size_kb = 8;
+ num_pages = flash_size_kb / page_size_kb;
stm32l4_info->bank1_sectors = num_pages;
- const bool use_dbank_bit = flash_size_in_kb == part_info->max_flash_size_kb;
+ use_dbank_bit = flash_size_kb == part_info->max_flash_size_kb;
if ((use_dbank_bit && (options & BIT(22))) ||
(!use_dbank_bit && (options & BIT(21)))) {
stm32l4_info->dual_bank_mode = true;
- page_size = 4096;
- num_pages = flash_size_in_kb / 4;
+ page_size_kb = 4;
+ num_pages = flash_size_kb / page_size_kb;
stm32l4_info->bank1_sectors = num_pages / 2;
}
break;
- case 0x495:
+ case 0x472: /* STM32L55/L56xx */
+ /* STM32L55/L56xx can be single/dual bank:
+ * if size = 512K check DBANK bit(22)
+ * if size = 256K check DB256K bit(21)
+ */
+ page_size_kb = 4;
+ num_pages = flash_size_kb / page_size_kb;
+ stm32l4_info->bank1_sectors = num_pages;
+ use_dbank_bit = flash_size_kb == part_info->max_flash_size_kb;
+ if ((use_dbank_bit && (options & BIT(22))) ||
+ (!use_dbank_bit && (options & BIT(21)))) {
+ stm32l4_info->dual_bank_mode = true;
+ page_size_kb = 2;
+ num_pages = flash_size_kb / page_size_kb;
+ stm32l4_info->bank1_sectors = num_pages / 2;
+ }
+ break;
+ case 0x495: /* STM32WB5x */
+ case 0x496: /* STM32WB3x */
/* single bank flash */
- page_size = 4096;
- num_pages = flash_size_in_kb / 4;
+ page_size_kb = 4;
+ num_pages = flash_size_kb / page_size_kb;
stm32l4_info->bank1_sectors = num_pages;
break;
default:
LOG_INFO("flash mode : %s-bank", stm32l4_info->dual_bank_mode ? "dual" : "single");
- const int gap_size = stm32l4_info->hole_sectors * page_size;
+ const int gap_size_kb = stm32l4_info->hole_sectors * page_size_kb;
- if (stm32l4_info->dual_bank_mode & gap_size) {
- LOG_INFO("gap detected starting from %0x08" PRIx32 " to %0x08" PRIx32,
- 0x8000000 + stm32l4_info->bank1_sectors * page_size,
- 0x8000000 + stm32l4_info->bank1_sectors * page_size + gap_size);
+ if (gap_size_kb != 0) {
+ LOG_INFO("gap detected from 0x%08x to 0x%08x",
+ STM32_FLASH_BANK_BASE + stm32l4_info->bank1_sectors
+ * page_size_kb * 1024,
+ STM32_FLASH_BANK_BASE + (stm32l4_info->bank1_sectors
+ * page_size_kb + gap_size_kb) * 1024 - 1);
}
- if (bank->sectors) {
- free(bank->sectors);
- bank->sectors = NULL;
- }
+ /* number of significant bits in WRPxxR differs per device,
+ * always right adjusted, on some devices non-implemented
+ * bits read as '0', on others as '1' ...
+ * notably G4 Cat. 2 implement only 6 bits, contradicting the RM
+ */
+
+ /* use *max_flash_size* instead of actual size as the trimmed versions
+ * certainly use the same number of bits
+ * max_flash_size is always power of two, so max_pages too
+ */
+ uint32_t max_pages = stm32l4_info->part_info->max_flash_size_kb / page_size_kb;
+ assert((max_pages & (max_pages - 1)) == 0);
+
+ /* in dual bank mode number of pages is doubled, but extra bit is bank selection */
+ stm32l4_info->wrpxxr_mask = ((max_pages >> (stm32l4_info->dual_bank_mode ? 1 : 0)) - 1);
+ assert((stm32l4_info->wrpxxr_mask & 0xFFFF0000) == 0);
+ LOG_DEBUG("WRPxxR mask 0x%04" PRIx16, (uint16_t)stm32l4_info->wrpxxr_mask);
- bank->size = flash_size_in_kb * 1024 + gap_size;
- bank->base = 0x08000000;
+ free(bank->sectors);
+
+ bank->size = (flash_size_kb + gap_size_kb) * 1024;
+ bank->base = STM32_FLASH_BANK_BASE;
bank->num_sectors = num_pages;
bank->sectors = malloc(sizeof(struct flash_sector) * bank->num_sectors);
if (bank->sectors == NULL) {
return ERROR_FAIL;
}
- for (i = 0; i < bank->num_sectors; i++) {
- bank->sectors[i].offset = i * page_size;
+ for (unsigned int i = 0; i < bank->num_sectors; i++) {
+ bank->sectors[i].offset = i * page_size_kb * 1024;
/* in dual bank configuration, if there is a gap between banks
* we fix up the sector offset to consider this gap */
if (i >= stm32l4_info->bank1_sectors && stm32l4_info->hole_sectors)
- bank->sectors[i].offset += gap_size;
- bank->sectors[i].size = page_size;
+ bank->sectors[i].offset += gap_size_kb * 1024;
+ bank->sectors[i].size = page_size_kb * 1024;
bank->sectors[i].is_erased = -1;
bank->sectors[i].is_protected = 1;
}
- stm32l4_info->probed = 1;
+ stm32l4_info->probed = true;
return ERROR_OK;
}
for (unsigned int i = 0; i < part_info->num_revs; i++) {
if (rev_id == part_info->revs[i].rev) {
rev_str = part_info->revs[i].str;
-
- if (rev_str != NULL) {
- snprintf(buf, buf_size, "%s - Rev: %s",
- part_info->device_str, rev_str);
- return ERROR_OK;
- }
+ break;
}
}
- snprintf(buf, buf_size, "%s - Rev: unknown (0x%04x)",
- part_info->device_str, rev_id);
+ int buf_len = snprintf(buf, buf_size, "%s - Rev %s : 0x%04x",
+ part_info->device_str, rev_str ? rev_str : "'unknown'", rev_id);
+
+ if (stm32l4_info->probed)
+ snprintf(buf + buf_len, buf_size - buf_len, " - %s-bank",
+ stm32l4_info->dual_bank_mode ? "Flash dual" : "Flash single");
+
return ERROR_OK;
} else {
- snprintf(buf, buf_size, "Cannot identify target as an STM32 L4 or WB device");
+ snprintf(buf, buf_size, "Cannot identify target as an %s device", device_families);
return ERROR_FAIL;
}
static int stm32l4_mass_erase(struct flash_bank *bank)
{
- int retval;
+ int retval, retval2;
struct target *target = bank->target;
struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
retval = stm32l4_unlock_reg(bank);
if (retval != ERROR_OK)
- return retval;
+ goto err_lock;
/* mass erase flash memory */
retval = stm32l4_wait_status_busy(bank, FLASH_ERASE_TIMEOUT / 10);
if (retval != ERROR_OK)
- return retval;
+ goto err_lock;
- retval = stm32l4_write_flash_reg(bank, STM32_FLASH_CR, action);
- if (retval != ERROR_OK)
- return retval;
- retval = stm32l4_write_flash_reg(bank, STM32_FLASH_CR, action | FLASH_STRT);
+ retval = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, action);
if (retval != ERROR_OK)
- return retval;
+ goto err_lock;
- retval = stm32l4_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
+ retval = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, action | FLASH_STRT);
if (retval != ERROR_OK)
- return retval;
+ goto err_lock;
+
+ retval = stm32l4_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
+
+err_lock:
+ retval2 = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, FLASH_LOCK);
- retval = stm32l4_write_flash_reg(bank, STM32_FLASH_CR, FLASH_LOCK);
if (retval != ERROR_OK)
return retval;
- return ERROR_OK;
+ return retval2;
}
COMMAND_HANDLER(stm32l4_handle_mass_erase_command)
{
- int i;
-
if (CMD_ARGC < 1) {
command_print(CMD, "stm32l4x mass_erase <STM32L4 bank>");
return ERROR_COMMAND_SYNTAX_ERROR;
retval = stm32l4_mass_erase(bank);
if (retval == ERROR_OK) {
/* set all sectors as erased */
- for (i = 0; i < bank->num_sectors; i++)
+ for (unsigned int i = 0; i < bank->num_sectors; i++)
bank->sectors[i].is_erased = 1;
command_print(CMD, "stm32l4x mass erase complete");
COMMAND_HANDLER(stm32l4_handle_option_load_command)
{
- if (CMD_ARGC < 1)
+ if (CMD_ARGC != 1)
return ERROR_COMMAND_SYNTAX_ERROR;
struct flash_bank *bank;
if (ERROR_OK != retval)
return retval;
- /* Write the OBLLAUNCH bit in CR -> Cause device "POR" and option bytes reload */
- retval = stm32l4_write_flash_reg(bank, STM32_FLASH_CR, FLASH_OBLLAUNCH);
+ /* Set OBL_LAUNCH bit in CR -> system reset and option bytes reload,
+ * but the RMs explicitly do *NOT* list this as power-on reset cause, and:
+ * "Note: If the read protection is set while the debugger is still
+ * connected through JTAG/SWD, apply a POR (power-on reset) instead of a system reset."
+ */
+ retval = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, FLASH_OBL_LAUNCH);
+
+ command_print(CMD, "stm32l4x option load completed. Power-on reset might be required");
+
+ /* Need to re-probe after change */
+ struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
+ stm32l4_info->probed = false;
- command_print(CMD, "stm32l4x option load (POR) completed.");
return retval;
}
}
/* set readout protection level 1 by erasing the RDP option byte */
- if (stm32l4_write_option(bank, STM32_FLASH_OPTR, 0, 0x000000FF) != ERROR_OK) {
+ struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
+ if (stm32l4_write_option(bank, stm32l4_info->flash_regs[STM32_FLASH_OPTR_INDEX], 0, 0x000000FF) != ERROR_OK) {
command_print(CMD, "%s failed to lock device", bank->driver->name);
return ERROR_OK;
}
return ERROR_TARGET_NOT_HALTED;
}
- if (stm32l4_write_option(bank, STM32_FLASH_OPTR, RDP_LEVEL_0, 0x000000FF) != ERROR_OK) {
+ struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
+ if (stm32l4_write_option(bank, stm32l4_info->flash_regs[STM32_FLASH_OPTR_INDEX],
+ RDP_LEVEL_0, 0x000000FF) != ERROR_OK) {
command_print(CMD, "%s failed to unlock device", bank->driver->name);
return ERROR_OK;
}
projects / fw / openocd / blobdiff