{
struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
- LOG_INFO("OTP memory bank #%d is disabled for write commands.",
+ LOG_INFO("OTP memory bank #%u is disabled for write commands.",
bank->bank_number);
stm32x_info->otp_unlocked = false;
return ERROR_OK;
struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
if (!stm32x_info->otp_unlocked) {
- LOG_INFO("OTP memory bank #%d is is enabled for write commands.",
+ LOG_INFO("OTP memory bank #%u is is enabled for write commands.",
bank->bank_number);
stm32x_info->otp_unlocked = true;
} else {
- LOG_WARNING("OTP memory bank #%d is is already enabled for write commands.",
+ LOG_WARNING("OTP memory bank #%u is is already enabled for write commands.",
bank->bank_number);
}
return ERROR_OK;
{
struct target *target = bank->target;
uint32_t lock_base;
- int i, retval;
+ int retval;
uint8_t lock;
lock_base = stm32x_otp_is_f7(bank) ? STM32F7_OTP_LOCK_BASE
: STM32F2_OTP_LOCK_BASE;
- for (i = 0; i < bank->num_sectors; i++) {
+ for (unsigned int i = 0; i < bank->num_sectors; i++) {
retval = target_read_u8(target, lock_base + i, &lock);
if (retval != ERROR_OK)
return retval;
return ERROR_OK;
}
-static int stm32x_otp_protect(struct flash_bank *bank, int first, int last)
+static int stm32x_otp_protect(struct flash_bank *bank, unsigned int first,
+ unsigned int last)
{
struct target *target = bank->target;
uint32_t lock_base;
int i, retval;
uint8_t lock;
- assert((0 <= first) && (first <= last) && (last < bank->num_sectors));
+ assert((first <= last) && (last < bank->num_sectors));
lock_base = stm32x_otp_is_f7(bank) ? STM32F7_OTP_LOCK_BASE
: STM32F2_OTP_LOCK_BASE;
return ERROR_OK;
}
-static int stm32x_erase(struct flash_bank *bank, int first, int last)
+static int stm32x_erase(struct flash_bank *bank, unsigned int first,
+ unsigned int last)
{
struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
struct target *target = bank->target;
- int i;
if (stm32x_is_otp(bank)) {
LOG_ERROR("Cannot erase OTP memory");
return ERROR_FAIL;
}
- assert((0 <= first) && (first <= last) && (last < bank->num_sectors));
+ assert((first <= last) && (last < bank->num_sectors));
if (bank->target->state != TARGET_HALTED) {
LOG_ERROR("Target not halted");
4. Wait for the BSY bit to be cleared
*/
- for (i = first; i <= last; i++) {
+ for (unsigned int i = first; i <= last; i++) {
unsigned int snb;
if (stm32x_info->has_large_mem && i >= 12)
snb = (i - 12) | 0x10;
return ERROR_OK;
}
-static int stm32x_protect(struct flash_bank *bank, int set, int first, int last)
+static int stm32x_protect(struct flash_bank *bank, int set, unsigned int first,
+ unsigned int last)
{
struct target *target = bank->target;
struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
return retval;
}
- for (int i = first; i <= last; i++) {
+ for (unsigned int i = first; i <= last; i++) {
if (set)
stm32x_info->option_bytes.protection &= ~(1 << i);
else
return target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
}
-static void setup_sector(struct flash_bank *bank, int i, int size)
+static void setup_sector(struct flash_bank *bank, unsigned int i,
+ unsigned int size)
{
assert(i < bank->num_sectors);
bank->sectors[i].offset = bank->size;
COMMAND_HANDLER(stm32x_handle_mass_erase_command)
{
- int i;
-
if (CMD_ARGC < 1) {
command_print(CMD, "stm32x mass_erase <bank>");
return ERROR_COMMAND_SYNTAX_ERROR;
retval = stm32x_mass_erase(bank);
if (retval == ERROR_OK) {
/* set all sectors as erased */
- for (i = 0; i < bank->num_sectors; i++)
+ for (unsigned int i = 0; i < bank->num_sectors; i++)
bank->sectors[i].is_erased = 1;
command_print(CMD, "stm32x mass erase complete");