};
static int stm32x_mass_erase(struct flash_bank *bank);
+static int stm32x_get_device_id(struct flash_bank *bank, uint32_t *device_id);
/* flash bank stm32x <base> <size> 0 0 <target#>
*/
return ERROR_COMMAND_SYNTAX_ERROR;
stm32x_info = malloc(sizeof(struct stm32x_flash_bank));
- bank->driver_priv = stm32x_info;
+ bank->driver_priv = stm32x_info;
stm32x_info->write_algorithm = NULL;
stm32x_info->probed = 0;
stm32x_info->has_dual_banks = false;
/* see contrib/loaders/flash/stm32f1x.S for src */
static const uint8_t stm32x_flash_write_code[] = {
- /* #define STM32_FLASH_CR_OFFSET 0x10 */
/* #define STM32_FLASH_SR_OFFSET 0x0C */
/* wait_fifo: */
0x16, 0x68, /* ldr r6, [r2, #0] */
0x00, 0x2e, /* cmp r6, #0 */
- 0x1a, 0xd0, /* beq exit */
+ 0x18, 0xd0, /* beq exit */
0x55, 0x68, /* ldr r5, [r2, #4] */
0xb5, 0x42, /* cmp r5, r6 */
0xf9, 0xd0, /* beq wait_fifo */
- 0x01, 0x26, /* movs r6, #1 */
- 0x06, 0x61, /* str r6, [r0, #STM32_FLASH_CR_OFFSET] */
0x2e, 0x88, /* ldrh r6, [r5, #0] */
0x26, 0x80, /* strh r6, [r4, #0] */
0x02, 0x35, /* adds r5, #2 */
0x01, 0x39, /* subs r1, r1, #1 */
0x00, 0x29, /* cmp r1, #0 */
0x02, 0xd0, /* beq exit */
- 0xe3, 0xe7, /* b wait_fifo */
+ 0xe5, 0xe7, /* b wait_fifo */
/* error: */
0x00, 0x20, /* movs r0, #0 */
0x50, 0x60, /* str r0, [r2, #4] */
}
};
- /* Set up working area. First word is write pointer, second word is read pointer,
- * rest is fifo data area. */
- uint32_t wp_addr = source->address;
- uint32_t rp_addr = source->address + 4;
- uint32_t fifo_start_addr = source->address + 8;
- uint32_t fifo_end_addr = source->address + source->size;
-
- uint32_t wp = fifo_start_addr;
- uint32_t rp = fifo_start_addr;
-
- retval = target_write_u32(target, wp_addr, wp);
- if (retval != ERROR_OK)
- return retval;
- retval = target_write_u32(target, rp_addr, rp);
- if (retval != ERROR_OK)
- return retval;
-
init_reg_param(®_params[0], "r0", 32, PARAM_IN_OUT); /* flash base (in), status (out) */
init_reg_param(®_params[1], "r1", 32, PARAM_OUT); /* count (halfword-16bit) */
init_reg_param(®_params[2], "r2", 32, PARAM_OUT); /* buffer start */
armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
armv7m_info.core_mode = ARMV7M_MODE_ANY;
- /* Start up algorithm on target and let it idle while writing the first chunk */
- retval = target_start_algorithm(target, 0, NULL, 5, reg_params,
- stm32x_info->write_algorithm->address,
- 0,
+ retval = target_run_flash_async_algorithm(target, buffer, count, 2,
+ 0, NULL,
+ 5, reg_params,
+ source->address, source->size,
+ stm32x_info->write_algorithm->address, 0,
&armv7m_info);
- if (retval != ERROR_OK) {
- LOG_ERROR("error starting stm32x flash write algorithm");
- goto cleanup;
- }
-
- while (count > 0) {
- retval = target_read_u32(target, rp_addr, &rp);
- if (retval != ERROR_OK) {
- LOG_ERROR("failed to get read pointer");
- break;
- }
-
- LOG_DEBUG("count 0x%"PRIx32" wp 0x%"PRIx32" rp 0x%"PRIx32, count, wp, rp);
-
- if (rp == 0) {
- LOG_ERROR("flash write algorithm aborted by target");
- retval = ERROR_FLASH_OPERATION_FAILED;
- break;
- }
-
- if ((rp & 1) || rp < fifo_start_addr || rp >= fifo_end_addr) {
- LOG_ERROR("corrupted fifo read pointer 0x%"PRIx32, rp);
- break;
- }
-
- /* Count the number of bytes available in the fifo without
- * crossing the wrap around. Make sure to not fill it completely,
- * because that would make wp == rp and that's the empty condition. */
- uint32_t thisrun_bytes;
- if (rp > wp)
- thisrun_bytes = rp - wp - 2;
- else if (rp > fifo_start_addr)
- thisrun_bytes = fifo_end_addr - wp;
- else
- thisrun_bytes = fifo_end_addr - wp - 2;
-
- if (thisrun_bytes == 0) {
- /* Throttle polling a bit if transfer is (much) faster than flash
- * programming. The exact delay shouldn't matter as long as it's
- * less than buffer size / flash speed. This is very unlikely to
- * run when using high latency connections such as USB. */
- alive_sleep(10);
- continue;
- }
-
- /* Limit to the amount of data we actually want to write */
- if (thisrun_bytes > count * 2)
- thisrun_bytes = count * 2;
-
- /* Write data to fifo */
- retval = target_write_buffer(target, wp, thisrun_bytes, buffer);
- if (retval != ERROR_OK)
- break;
-
- /* Update counters and wrap write pointer */
- buffer += thisrun_bytes;
- count -= thisrun_bytes / 2;
- wp += thisrun_bytes;
- if (wp >= fifo_end_addr)
- wp = fifo_start_addr;
-
- /* Store updated write pointer to target */
- retval = target_write_u32(target, wp_addr, wp);
- if (retval != ERROR_OK)
- break;
- }
-
- if (retval != ERROR_OK) {
- /* abort flash write algorithm on target */
- target_write_u32(target, wp_addr, 0);
- }
-
- int retval2 = target_wait_algorithm(target, 0, NULL, 5, reg_params,
- 0, 10000, &armv7m_info);
- if (retval2 != ERROR_OK) {
- LOG_ERROR("error waiting for stm32x flash write algorithm");
- retval = retval2;
- }
if (retval == ERROR_FLASH_OPERATION_FAILED) {
LOG_ERROR("flash write failed at address 0x%"PRIx32,
if (buf_get_u32(reg_params[0].value, 0, 32) & FLASH_PGERR) {
LOG_ERROR("flash memory not erased before writing");
/* Clear but report errors */
- target_write_u32(target, STM32_FLASH_SR_B0, FLASH_PGERR);
+ target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), FLASH_PGERR);
}
if (buf_get_u32(reg_params[0].value, 0, 32) & FLASH_WRPRTERR) {
LOG_ERROR("flash memory write protected");
/* Clear but report errors */
- target_write_u32(target, STM32_FLASH_SR_B0, FLASH_WRPRTERR);
+ target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), FLASH_WRPRTERR);
}
}
-cleanup:
target_free_working_area(target, source);
target_free_working_area(target, stm32x_info->write_algorithm);
if (retval != ERROR_OK)
return retval;
+ retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PG);
+ if (retval != ERROR_OK)
+ return retval;
+
/* multiple half words (2-byte) to be programmed? */
if (words_remaining > 0) {
/* try using a block write */
}
if ((retval != ERROR_OK) && (retval != ERROR_TARGET_RESOURCE_NOT_AVAILABLE))
- return retval;
+ goto reset_pg_and_lock;
while (words_remaining > 0) {
uint16_t value;
memcpy(&value, buffer + bytes_written, sizeof(uint16_t));
- retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PG);
- if (retval != ERROR_OK)
- return retval;
retval = target_write_u16(target, address, value);
if (retval != ERROR_OK)
- return retval;
+ goto reset_pg_and_lock;
retval = stm32x_wait_status_busy(bank, 5);
if (retval != ERROR_OK)
- return retval;
+ goto reset_pg_and_lock;
bytes_written += 2;
words_remaining--;
uint16_t value = 0xffff;
memcpy(&value, buffer + bytes_written, bytes_remaining);
- retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PG);
- if (retval != ERROR_OK)
- return retval;
retval = target_write_u16(target, address, value);
if (retval != ERROR_OK)
- return retval;
+ goto reset_pg_and_lock;
retval = stm32x_wait_status_busy(bank, 5);
if (retval != ERROR_OK)
- return retval;
+ goto reset_pg_and_lock;
}
- return target_write_u32(target, STM32_FLASH_CR_B0, FLASH_LOCK);
+ return target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
+
+reset_pg_and_lock:
+ target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
+ return retval;
}
-static int stm32x_probe(struct flash_bank *bank)
+static int stm32x_get_device_id(struct flash_bank *bank, uint32_t *device_id)
{
+ /* This check the device CPUID core register to detect
+ * the M0 from the M3 devices. */
+
struct target *target = bank->target;
+ uint32_t cpuid, device_id_register = 0;
+
+ /* Get the CPUID from the ARM Core
+ * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0432c/DDI0432C_cortex_m0_r0p0_trm.pdf 4.2.1 */
+ int retval = target_read_u32(target, 0xE000ED00, &cpuid);
+ if (retval != ERROR_OK)
+ return retval;
+
+ if (((cpuid >> 4) & 0xFFF) == 0xC20) {
+ /* 0xC20 is M0 devices */
+ device_id_register = 0x40015800;
+ } else if (((cpuid >> 4) & 0xFFF) == 0xC23) {
+ /* 0xC23 is M3 devices */
+ device_id_register = 0xE0042000;
+ } else if (((cpuid >> 4) & 0xFFF) == 0xC24) {
+ /* 0xC24 is M4 devices */
+ device_id_register = 0xE0042000;
+ } else {
+ LOG_ERROR("Cannot identify target as a stm32x");
+ return ERROR_FAIL;
+ }
+
+ /* read stm32 device id register */
+ retval = target_read_u32(target, device_id_register, device_id);
+ if (retval != ERROR_OK)
+ return retval;
+
+ return retval;
+}
+
+static int stm32x_get_flash_size(struct flash_bank *bank, uint16_t *flash_size_in_kb)
+{
+ struct target *target = bank->target;
+ uint32_t cpuid, flash_size_reg;
+
+ int retval = target_read_u32(target, 0xE000ED00, &cpuid);
+ if (retval != ERROR_OK)
+ return retval;
+
+ if (((cpuid >> 4) & 0xFFF) == 0xC20) {
+ /* 0xC20 is M0 devices */
+ flash_size_reg = 0x1FFFF7CC;
+ } else if (((cpuid >> 4) & 0xFFF) == 0xC23) {
+ /* 0xC23 is M3 devices */
+ flash_size_reg = 0x1FFFF7E0;
+ } else if (((cpuid >> 4) & 0xFFF) == 0xC24) {
+ /* 0xC24 is M4 devices */
+ flash_size_reg = 0x1FFFF7CC;
+ } else {
+ LOG_ERROR("Cannot identify target as a stm32x");
+ return ERROR_FAIL;
+ }
+
+ retval = target_read_u16(target, flash_size_reg, flash_size_in_kb);
+ if (retval != ERROR_OK)
+ return retval;
+
+ return retval;
+}
+
+static int stm32x_probe(struct flash_bank *bank)
+{
struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
int i;
uint16_t flash_size_in_kb;
stm32x_info->register_base = FLASH_REG_BASE_B0;
/* read stm32 device id register */
- int retval = target_read_u32(target, 0xE0042000, &device_id);
+ int retval = stm32x_get_device_id(bank, &device_id);
if (retval != ERROR_OK)
return retval;
+
LOG_INFO("device id = 0x%08" PRIx32 "", device_id);
/* get flash size from target. */
- retval = target_read_u16(target, 0x1FFFF7E0, &flash_size_in_kb);
+ retval = stm32x_get_flash_size(bank, &flash_size_in_kb);
if (retval != ERROR_OK) {
LOG_WARNING("failed reading flash size, default to max target family");
/* failed reading flash size, default to max target family */
flash_size_in_kb = 0xffff;
}
+ /* some variants read 0 for flash size register
+ * use a max flash size as a default */
+ if (flash_size_in_kb == 0)
+ flash_size_in_kb = 0xffff;
+
if ((device_id & 0xfff) == 0x410) {
/* medium density - we have 1k pages
* 4 pages for a protection area */
/* check for early silicon */
if (flash_size_in_kb == 0xffff) {
- /* number of sectors may be incorrrect on early silicon */
+ /* number of sectors may be incorrect on early silicon */
LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 128k flash");
flash_size_in_kb = 128;
}
+ } else if ((device_id & 0xfff) == 0x422) {
+ /* stm32f30x - we have 2k pages
+ * 2 pages for a protection area */
+ page_size = 2048;
+ stm32x_info->ppage_size = 2;
+
+ /* check for early silicon */
+ if (flash_size_in_kb == 0xffff) {
+ LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 256k flash");
+ flash_size_in_kb = 256;
+ }
} else if ((device_id & 0xfff) == 0x428) {
/* value line High density - we have 2k pages
* 4 pages for a protection area */
/* check for early silicon */
if (flash_size_in_kb == 0xffff) {
- /* number of sectors may be incorrrect on early silicon */
+ /* number of sectors may be incorrect on early silicon */
LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 128k flash");
flash_size_in_kb = 128;
}
/* check for early silicon */
if (flash_size_in_kb == 0xffff) {
- /* number of sectors may be incorrrect on early silicon */
+ /* number of sectors may be incorrect on early silicon */
LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 1024k flash");
flash_size_in_kb = 1024;
}
stm32x_info->register_base = FLASH_REG_BASE_B1;
base_address = 0x08080000;
}
+ } else if ((device_id & 0xfff) == 0x432) {
+ /* stm32f37x - we have 2k pages
+ * 2 pages for a protection area */
+ page_size = 2048;
+ stm32x_info->ppage_size = 2;
+
+ /* check for early silicon */
+ if (flash_size_in_kb == 0xffff) {
+ LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 256k flash");
+ flash_size_in_kb = 256;
+ }
+ } else if ((device_id & 0xfff) == 0x440) {
+ /* stm32f0x - we have 1k pages
+ * 4 pages for a protection area */
+ page_size = 1024;
+ stm32x_info->ppage_size = 4;
+
+ /* check for early silicon */
+ if (flash_size_in_kb == 0xffff) {
+ /* number of sectors incorrect on revZ */
+ LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 64k flash");
+ flash_size_in_kb = 64;
+ }
} else {
LOG_WARNING("Cannot identify target as a STM32 family.");
return ERROR_FAIL;
static int get_stm32x_info(struct flash_bank *bank, char *buf, int buf_size)
{
- struct target *target = bank->target;
uint32_t device_id;
int printed;
- /* read stm32 device id register */
- int retval = target_read_u32(target, 0xE0042000, &device_id);
+ /* read stm32 device id register */
+ int retval = stm32x_get_device_id(bank, &device_id);
if (retval != ERROR_OK)
return retval;
snprintf(buf, buf_size, "Z");
break;
+ default:
+ snprintf(buf, buf_size, "unknown");
+ break;
+ }
+ } else if ((device_id & 0xfff) == 0x422) {
+ printed = snprintf(buf, buf_size, "stm32f30x - Rev: ");
+ buf += printed;
+ buf_size -= printed;
+
+ switch (device_id >> 16) {
+ case 0x1000:
+ snprintf(buf, buf_size, "1.0");
+ break;
+
default:
snprintf(buf, buf_size, "unknown");
break;
snprintf(buf, buf_size, "A");
break;
+ default:
+ snprintf(buf, buf_size, "unknown");
+ break;
+ }
+ } else if ((device_id & 0xfff) == 0x432) {
+ printed = snprintf(buf, buf_size, "stm32f37x - Rev: ");
+ buf += printed;
+ buf_size -= printed;
+
+ switch (device_id >> 16) {
+ case 0x1000:
+ snprintf(buf, buf_size, "1.0");
+ break;
+
+ default:
+ snprintf(buf, buf_size, "unknown");
+ break;
+ }
+ } else if ((device_id & 0xfff) == 0x440) {
+ printed = snprintf(buf, buf_size, "stm32f0x - Rev: ");
+ buf += printed;
+ buf_size -= printed;
+
+ switch (device_id >> 16) {
+ case 0x1000:
+ snprintf(buf, buf_size, "1.0");
+ break;
+
+ case 0x2000:
+ snprintf(buf, buf_size, "2.0");
+ break;
+
default:
snprintf(buf, buf_size, "unknown");
break;
.read = default_flash_read,
.probe = stm32x_probe,
.auto_probe = stm32x_auto_probe,
- .erase_check = default_flash_mem_blank_check,
+ .erase_check = default_flash_blank_check,
.protect_check = stm32x_protect_check,
.info = get_stm32x_info,
};
projects / fw / openocd / blobdiff