+// SPDX-License-Identifier: GPL-2.0-or-later
+
/***************************************************************************
* Copyright (C) 2005 by Dominic Rath *
* Dominic.Rath@gmx.de *
* *
* Copyright (C) 2008 by John McCarthy *
* jgmcc@magma.ca *
- * *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program. If not, see <http://www.gnu.org/licenses/>. *
***************************************************************************/
#ifdef HAVE_CONFIG_H
* Note: These macros only work for KSEG0/KSEG1 addresses.
*/
-#define Virt2Phys(v) ((v) & 0x1FFFFFFF)
+#define virt2phys(v) ((v) & 0x1FFFFFFF)
/* pic32mx configuration register locations */
-#define PIC32MX_DEVCFG0_1xx_2xx 0xBFC00BFC
+#define PIC32MX_DEVCFG0_1XX_2XX 0xBFC00BFC
#define PIC32MX_DEVCFG0 0xBFC02FFC
#define PIC32MX_DEVCFG1 0xBFC02FF8
#define PIC32MX_DEVCFG2 0xBFC02FF4
#define NVMKEY1 0xAA996655
#define NVMKEY2 0x556699AA
-#define MX_1xx_2xx 1 /* PIC32mx1xx/2xx */
-#define MX_17x_27x 2 /* PIC32mx17x/27x */
+#define MX_1XX_2XX 1 /* PIC32mx1xx/2xx */
+#define MX_17X_27X 2 /* PIC32mx17x/27x */
struct pic32mx_flash_bank {
bool probed;
}
switch (pic32mx_info->dev_type) {
- case MX_1xx_2xx:
- case MX_17x_27x:
- config0_address = PIC32MX_DEVCFG0_1xx_2xx;
+ case MX_1XX_2XX:
+ case MX_17X_27X:
+ config0_address = PIC32MX_DEVCFG0_1XX_2XX;
break;
default:
config0_address = PIC32MX_DEVCFG0;
if ((devcfg0 & (1 << 28)) == 0) /* code protect bit */
num_pages = 0xffff; /* All pages protected */
- else if (Virt2Phys(bank->base) == PIC32MX_PHYS_BOOT_FLASH) {
+ else if (virt2phys(bank->base) == PIC32MX_PHYS_BOOT_FLASH) {
if (devcfg0 & (1 << 24))
num_pages = 0; /* All pages unprotected */
else
} else {
/* pgm flash */
switch (pic32mx_info->dev_type) {
- case MX_1xx_2xx:
+ case MX_1XX_2XX:
num_pages = (~devcfg0 >> 10) & 0x7f;
break;
- case MX_17x_27x:
+ case MX_17X_27X:
num_pages = (~devcfg0 >> 10) & 0x1ff;
break;
default:
}
if ((first == 0) && (last == (bank->num_sectors - 1))
- && (Virt2Phys(bank->base) == PIC32MX_PHYS_PGM_FLASH)) {
+ && (virt2phys(bank->base) == PIC32MX_PHYS_PGM_FLASH)) {
/* this will only erase the Program Flash (PFM), not the Boot Flash (BFM)
* we need to use the MTAP to perform a full erase */
LOG_DEBUG("Erasing entire program flash");
}
for (unsigned int i = first; i <= last; i++) {
- target_write_u32(target, PIC32MX_NVMADDR, Virt2Phys(bank->base + bank->sectors[i].offset));
+ target_write_u32(target, PIC32MX_NVMADDR, virt2phys(bank->base + bank->sectors[i].offset));
status = pic32mx_nvm_exec(bank, NVMCON_OP_PAGE_ERASE, 10);
return ERROR_FLASH_OPERATION_FAILED;
if (status & NVMCON_LVDERR)
return ERROR_FLASH_OPERATION_FAILED;
- bank->sectors[i].is_erased = 1;
}
return ERROR_OK;
/* Change values for counters and row size, depending on variant */
switch (pic32mx_info->dev_type) {
- case MX_1xx_2xx:
- case MX_17x_27x:
+ case MX_1XX_2XX:
+ case MX_17X_27X:
/* 128 byte row */
pic32mx_flash_write_code[8] = 0x2CD30020;
pic32mx_flash_write_code[14] = 0x24840080;
uint8_t *new_buffer = NULL;
if (row_offset && (count >= (row_size / 4))) {
new_buffer = malloc(buffer_size);
- if (new_buffer == NULL) {
+ if (!new_buffer) {
LOG_ERROR("Out of memory");
return ERROR_FAIL;
}
break;
}
- buf_set_u32(reg_params[0].value, 0, 32, Virt2Phys(source->address));
- buf_set_u32(reg_params[1].value, 0, 32, Virt2Phys(address));
+ buf_set_u32(reg_params[0].value, 0, 32, virt2phys(source->address));
+ buf_set_u32(reg_params[1].value, 0, 32, virt2phys(address));
buf_set_u32(reg_params[2].value, 0, 32, thisrun_count + row_offset / 4);
retval = target_run_algorithm(target, 0, NULL, 3, reg_params,
{
struct target *target = bank->target;
- target_write_u32(target, PIC32MX_NVMADDR, Virt2Phys(address));
+ target_write_u32(target, PIC32MX_NVMADDR, virt2phys(address));
target_write_u32(target, PIC32MX_NVMDATA, word);
return pic32mx_nvm_exec(bank, NVMCON_OP_WORD_PROG, 5);
}
/* Check for PIC32mx1xx/2xx */
- for (i = 0; pic32mx_devs[i].name != NULL; i++) {
+ for (i = 0; pic32mx_devs[i].name; i++) {
if (pic32mx_devs[i].devid == (device_id & 0x0fffffff)) {
if ((pic32mx_devs[i].name[0] == '1') || (pic32mx_devs[i].name[0] == '2'))
- pic32mx_info->dev_type = (pic32mx_devs[i].name[1] == '7') ? MX_17x_27x : MX_1xx_2xx;
+ pic32mx_info->dev_type = (pic32mx_devs[i].name[1] == '7') ? MX_17X_27X : MX_1XX_2XX;
break;
}
}
switch (pic32mx_info->dev_type) {
- case MX_1xx_2xx:
- case MX_17x_27x:
+ case MX_1XX_2XX:
+ case MX_17X_27X:
page_size = 1024;
break;
default:
break;
}
- if (Virt2Phys(bank->base) == PIC32MX_PHYS_BOOT_FLASH) {
+ if (virt2phys(bank->base) == PIC32MX_PHYS_BOOT_FLASH) {
/* 0x1FC00000: Boot flash size */
#if 0
/* for some reason this register returns 8k for the boot bank size
#else
/* fixed 12k boot bank - see comments above */
switch (pic32mx_info->dev_type) {
- case MX_1xx_2xx:
- case MX_17x_27x:
+ case MX_1XX_2XX:
+ case MX_17X_27X:
num_pages = (3 * 1024);
break;
default:
/* read the flash size from the device */
if (target_read_u32(target, PIC32MX_BMXPFMSZ, &num_pages) != ERROR_OK) {
switch (pic32mx_info->dev_type) {
- case MX_1xx_2xx:
- case MX_17x_27x:
+ case MX_1XX_2XX:
+ case MX_17X_27X:
LOG_WARNING("PIC32MX flash size failed, probe inaccurate - assuming 32k flash");
num_pages = (32 * 1024);
break;
}
}
- LOG_INFO("flash size = %" PRIu32 "kbytes", num_pages / 1024);
+ LOG_INFO("flash size = %" PRIu32 " KiB", num_pages / 1024);
free(bank->sectors);
return pic32mx_probe(bank);
}
-static int pic32mx_info(struct flash_bank *bank, char *buf, int buf_size)
+static int pic32mx_info(struct flash_bank *bank, struct command_invocation *cmd)
{
struct target *target = bank->target;
struct mips32_common *mips32 = target->arch_info;
struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
uint32_t device_id;
- int printed = 0, i;
device_id = ejtag_info->idcode;
if (((device_id >> 1) & 0x7ff) != PIC32MX_MANUF_ID) {
- snprintf(buf, buf_size,
- "Cannot identify target as a PIC32MX family (manufacturer 0x%03x != 0x%03x)\n",
- (unsigned)((device_id >> 1) & 0x7ff),
- PIC32MX_MANUF_ID);
+ command_print_sameline(cmd,
+ "Cannot identify target as a PIC32MX family (manufacturer 0x%03x != 0x%03x)\n",
+ (unsigned)((device_id >> 1) & 0x7ff),
+ PIC32MX_MANUF_ID);
return ERROR_FLASH_OPERATION_FAILED;
}
- for (i = 0; pic32mx_devs[i].name != NULL; i++) {
+ int i;
+ for (i = 0; pic32mx_devs[i].name; i++) {
if (pic32mx_devs[i].devid == (device_id & 0x0fffffff)) {
- printed = snprintf(buf, buf_size, "PIC32MX%s", pic32mx_devs[i].name);
+ command_print_sameline(cmd, "PIC32MX%s", pic32mx_devs[i].name);
break;
}
}
- if (pic32mx_devs[i].name == NULL)
- printed = snprintf(buf, buf_size, "Unknown");
+ if (!pic32mx_devs[i].name)
+ command_print_sameline(cmd, "Unknown");
- buf += printed;
- buf_size -= printed;
- snprintf(buf, buf_size, " Ver: 0x%02x",
+ command_print_sameline(cmd, " Ver: 0x%02x",
(unsigned)((device_id >> 28) & 0xf));
return ERROR_OK;
struct flash_bank *bank;
int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 2, &bank);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
if (address < bank->base || address >= (bank->base + bank->size)) {
struct flash_bank *bank;
int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
target = bank->target;
projects / fw / openocd / blobdiff