+// SPDX-License-Identifier: GPL-2.0-or-later
+
/***************************************************************************
* Copyright (C) 2005 by Dominic Rath *
* Dominic.Rath@gmx.de *
* *
* Copyright (C) 2008 by John McCarthy *
* jgmcc@magma.ca *
- * *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
***************************************************************************/
#ifdef HAVE_CONFIG_H
* Note: These macros only work for KSEG0/KSEG1 addresses.
*/
-#define Virt2Phys(v) ((v) & 0x1FFFFFFF)
+#define virt2phys(v) ((v) & 0x1FFFFFFF)
/* pic32mx configuration register locations */
-#define PIC32MX_DEVCFG0_1_2 0xBFC00BFC
+#define PIC32MX_DEVCFG0_1XX_2XX 0xBFC00BFC
#define PIC32MX_DEVCFG0 0xBFC02FFC
#define PIC32MX_DEVCFG1 0xBFC02FF8
#define PIC32MX_DEVCFG2 0xBFC02FF4
#define NVMKEY1 0xAA996655
#define NVMKEY2 0x556699AA
-#define MX_1_2 1 /* PIC32mx1xx/2xx */
+#define MX_1XX_2XX 1 /* PIC32mx1xx/2xx */
+#define MX_17X_27X 2 /* PIC32mx17x/27x */
struct pic32mx_flash_bank {
- int probed;
+ bool probed;
int dev_type; /* Default 0. 1 for Pic32MX1XX/2XX variant */
};
/*
- * DEVID values as per PIC32MX Flash Programming Specification Rev J
+ * DEVID values as per PIC32MX Flash Programming Specification Rev N
*/
static const struct pic32mx_devs_s {
{0x04D06053, "150F128B"},
{0x04D08053, "150F128C"},
{0x04D0A053, "150F128D"},
+ {0x06610053, "170F256B"},
+ {0x0661A053, "170F256D"},
{0x04A01053, "210F016B"},
{0x04A03053, "210F016C"},
{0x04A05053, "210F016D"},
{0x04D00053, "250F128B"},
{0x04D02053, "250F128C"},
{0x04D04053, "250F128D"},
+ {0x06600053, "270F256B"},
+ {0x0660A053, "270F256D"},
+ {0x05600053, "330F064H"},
+ {0x05601053, "330F064L"},
+ {0x05602053, "430F064H"},
+ {0x05603053, "430F064L"},
+ {0x0570C053, "350F128H"},
+ {0x0570D053, "350F128L"},
+ {0x0570E053, "450F128H"},
+ {0x0570F053, "450F128L"},
+ {0x05704053, "350F256H"},
+ {0x05705053, "350F256L"},
+ {0x05706053, "450F256H"},
+ {0x05707053, "450F256L"},
+ {0x05808053, "370F512H"},
+ {0x05809053, "370F512L"},
+ {0x0580A053, "470F512H"},
+ {0x0580B053, "470F512L"},
{0x00938053, "360F512L"},
{0x00934053, "360F256L"},
{0x0092D053, "340F128L"},
pic32mx_info = malloc(sizeof(struct pic32mx_flash_bank));
bank->driver_priv = pic32mx_info;
- pic32mx_info->probed = 0;
+ pic32mx_info->probed = false;
pic32mx_info->dev_type = 0;
return ERROR_OK;
uint32_t config0_address;
uint32_t devcfg0;
- int s;
- int num_pages;
+ unsigned int s, num_pages;
if (target->state != TARGET_HALTED) {
LOG_ERROR("Target not halted");
return ERROR_TARGET_NOT_HALTED;
}
- if (pic32mx_info->dev_type == MX_1_2)
- config0_address = PIC32MX_DEVCFG0_1_2;
- else
+ switch (pic32mx_info->dev_type) {
+ case MX_1XX_2XX:
+ case MX_17X_27X:
+ config0_address = PIC32MX_DEVCFG0_1XX_2XX;
+ break;
+ default:
config0_address = PIC32MX_DEVCFG0;
+ break;
+ }
target_read_u32(target, config0_address, &devcfg0);
if ((devcfg0 & (1 << 28)) == 0) /* code protect bit */
num_pages = 0xffff; /* All pages protected */
- else if (Virt2Phys(bank->base) == PIC32MX_PHYS_BOOT_FLASH) {
+ else if (virt2phys(bank->base) == PIC32MX_PHYS_BOOT_FLASH) {
if (devcfg0 & (1 << 24))
num_pages = 0; /* All pages unprotected */
else
num_pages = 0xffff; /* All pages protected */
} else {
/* pgm flash */
- if (pic32mx_info->dev_type == MX_1_2)
- num_pages = (~devcfg0 >> 10) & 0x3f;
- else
+ switch (pic32mx_info->dev_type) {
+ case MX_1XX_2XX:
+ num_pages = (~devcfg0 >> 10) & 0x7f;
+ break;
+ case MX_17X_27X:
+ num_pages = (~devcfg0 >> 10) & 0x1ff;
+ break;
+ default:
num_pages = (~devcfg0 >> 12) & 0xff;
+ break;
+ }
}
for (s = 0; s < bank->num_sectors && s < num_pages; s++)
return ERROR_OK;
}
-static int pic32mx_erase(struct flash_bank *bank, int first, int last)
+static int pic32mx_erase(struct flash_bank *bank, unsigned int first,
+ unsigned int last)
{
struct target *target = bank->target;
- int i;
uint32_t status;
if (bank->target->state != TARGET_HALTED) {
}
if ((first == 0) && (last == (bank->num_sectors - 1))
- && (Virt2Phys(bank->base) == PIC32MX_PHYS_PGM_FLASH)) {
+ && (virt2phys(bank->base) == PIC32MX_PHYS_PGM_FLASH)) {
/* this will only erase the Program Flash (PFM), not the Boot Flash (BFM)
* we need to use the MTAP to perform a full erase */
LOG_DEBUG("Erasing entire program flash");
return ERROR_OK;
}
- for (i = first; i <= last; i++) {
- target_write_u32(target, PIC32MX_NVMADDR, Virt2Phys(bank->base + bank->sectors[i].offset));
+ for (unsigned int i = first; i <= last; i++) {
+ target_write_u32(target, PIC32MX_NVMADDR, virt2phys(bank->base + bank->sectors[i].offset));
status = pic32mx_nvm_exec(bank, NVMCON_OP_PAGE_ERASE, 10);
return ERROR_FLASH_OPERATION_FAILED;
if (status & NVMCON_LVDERR)
return ERROR_FLASH_OPERATION_FAILED;
- bank->sectors[i].is_erased = 1;
}
return ERROR_OK;
}
-static int pic32mx_protect(struct flash_bank *bank, int set, int first, int last)
+static int pic32mx_protect(struct flash_bank *bank, int set, unsigned int first,
+ unsigned int last)
{
struct target *target = bank->target;
return ERROR_OK;
}
-/* see contib/loaders/flash/pic32mx.s for src */
+/* see contrib/loaders/flash/pic32mx.s for src */
static uint32_t pic32mx_flash_write_code[] = {
/* write: */
&write_algorithm) != ERROR_OK) {
LOG_WARNING("no working area available, can't do block memory writes");
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
- };
+ }
/* Change values for counters and row size, depending on variant */
- if (pic32mx_info->dev_type == MX_1_2) {
+ switch (pic32mx_info->dev_type) {
+ case MX_1XX_2XX:
+ case MX_17X_27X:
/* 128 byte row */
pic32mx_flash_write_code[8] = 0x2CD30020;
pic32mx_flash_write_code[14] = 0x24840080;
pic32mx_flash_write_code[15] = 0x24A50080;
pic32mx_flash_write_code[17] = 0x24C6FFE0;
row_size = 128;
- } else {
+ break;
+ default:
/* 512 byte row */
pic32mx_flash_write_code[8] = 0x2CD30080;
pic32mx_flash_write_code[14] = 0x24840200;
pic32mx_flash_write_code[15] = 0x24A50200;
pic32mx_flash_write_code[17] = 0x24C6FF80;
row_size = 512;
+ break;
}
uint8_t code[sizeof(pic32mx_flash_write_code)];
uint8_t *new_buffer = NULL;
if (row_offset && (count >= (row_size / 4))) {
new_buffer = malloc(buffer_size);
- if (new_buffer == NULL) {
+ if (!new_buffer) {
LOG_ERROR("Out of memory");
return ERROR_FAIL;
}
break;
}
- buf_set_u32(reg_params[0].value, 0, 32, Virt2Phys(source->address));
- buf_set_u32(reg_params[1].value, 0, 32, Virt2Phys(address));
+ buf_set_u32(reg_params[0].value, 0, 32, virt2phys(source->address));
+ buf_set_u32(reg_params[1].value, 0, 32, virt2phys(address));
buf_set_u32(reg_params[2].value, 0, 32, thisrun_count + row_offset / 4);
retval = target_run_algorithm(target, 0, NULL, 3, reg_params,
destroy_reg_param(®_params[1]);
destroy_reg_param(®_params[2]);
- if (new_buffer != NULL)
- free(new_buffer);
+ free(new_buffer);
return retval;
}
{
struct target *target = bank->target;
- target_write_u32(target, PIC32MX_NVMADDR, Virt2Phys(address));
+ target_write_u32(target, PIC32MX_NVMADDR, virt2phys(address));
target_write_u32(target, PIC32MX_NVMDATA, word);
return pic32mx_nvm_exec(bank, NVMCON_OP_WORD_PROG, 5);
return ERROR_TARGET_NOT_HALTED;
}
- LOG_DEBUG("writing to flash at address 0x%08" PRIx32 " at offset 0x%8.8" PRIx32
+ LOG_DEBUG("writing to flash at address " TARGET_ADDR_FMT " at offset 0x%8.8" PRIx32
" count: 0x%8.8" PRIx32 "", bank->base, offset, count);
if (offset & 0x3) {
uint32_t device_id;
int page_size;
- pic32mx_info->probed = 0;
+ pic32mx_info->probed = false;
device_id = ejtag_info->idcode;
LOG_INFO("device id = 0x%08" PRIx32 " (manuf 0x%03x dev 0x%04x, ver 0x%02x)",
}
/* Check for PIC32mx1xx/2xx */
- for (i = 0; pic32mx_devs[i].name != NULL; i++) {
+ for (i = 0; pic32mx_devs[i].name; i++) {
if (pic32mx_devs[i].devid == (device_id & 0x0fffffff)) {
- if ((*(pic32mx_devs[i].name) == '1') || (*(pic32mx_devs[i].name) == '2'))
- pic32mx_info->dev_type = MX_1_2;
+ if ((pic32mx_devs[i].name[0] == '1') || (pic32mx_devs[i].name[0] == '2'))
+ pic32mx_info->dev_type = (pic32mx_devs[i].name[1] == '7') ? MX_17X_27X : MX_1XX_2XX;
break;
}
}
- if (pic32mx_info->dev_type == MX_1_2)
+ switch (pic32mx_info->dev_type) {
+ case MX_1XX_2XX:
+ case MX_17X_27X:
page_size = 1024;
- else
+ break;
+ default:
page_size = 4096;
+ break;
+ }
-
- if (Virt2Phys(bank->base) == PIC32MX_PHYS_BOOT_FLASH) {
+ if (virt2phys(bank->base) == PIC32MX_PHYS_BOOT_FLASH) {
/* 0x1FC00000: Boot flash size */
#if 0
/* for some reason this register returns 8k for the boot bank size
}
#else
/* fixed 12k boot bank - see comments above */
- if (pic32mx_info->dev_type == MX_1_2)
+ switch (pic32mx_info->dev_type) {
+ case MX_1XX_2XX:
+ case MX_17X_27X:
num_pages = (3 * 1024);
- else
+ break;
+ default:
num_pages = (12 * 1024);
+ break;
+ }
#endif
} else {
/* read the flash size from the device */
if (target_read_u32(target, PIC32MX_BMXPFMSZ, &num_pages) != ERROR_OK) {
- if (pic32mx_info->dev_type == MX_1_2) {
+ switch (pic32mx_info->dev_type) {
+ case MX_1XX_2XX:
+ case MX_17X_27X:
LOG_WARNING("PIC32MX flash size failed, probe inaccurate - assuming 32k flash");
num_pages = (32 * 1024);
- } else {
+ break;
+ default:
LOG_WARNING("PIC32MX flash size failed, probe inaccurate - assuming 512k flash");
num_pages = (512 * 1024);
+ break;
}
}
}
- LOG_INFO("flash size = %" PRId32 "kbytes", num_pages / 1024);
+ LOG_INFO("flash size = %" PRIu32 " KiB", num_pages / 1024);
- if (bank->sectors) {
- free(bank->sectors);
- bank->sectors = NULL;
- }
+ free(bank->sectors);
/* calculate numbers of pages */
num_pages /= page_size;
bank->sectors[i].is_protected = 1;
}
- pic32mx_info->probed = 1;
+ pic32mx_info->probed = true;
return ERROR_OK;
}
return pic32mx_probe(bank);
}
-static int pic32mx_info(struct flash_bank *bank, char *buf, int buf_size)
+static int pic32mx_info(struct flash_bank *bank, struct command_invocation *cmd)
{
struct target *target = bank->target;
struct mips32_common *mips32 = target->arch_info;
struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
uint32_t device_id;
- int printed = 0, i;
device_id = ejtag_info->idcode;
if (((device_id >> 1) & 0x7ff) != PIC32MX_MANUF_ID) {
- snprintf(buf, buf_size,
- "Cannot identify target as a PIC32MX family (manufacturer 0x%03d != 0x%03d)\n",
- (unsigned)((device_id >> 1) & 0x7ff),
- PIC32MX_MANUF_ID);
+ command_print_sameline(cmd,
+ "Cannot identify target as a PIC32MX family (manufacturer 0x%03x != 0x%03x)\n",
+ (unsigned)((device_id >> 1) & 0x7ff),
+ PIC32MX_MANUF_ID);
return ERROR_FLASH_OPERATION_FAILED;
}
- for (i = 0; pic32mx_devs[i].name != NULL; i++) {
+ int i;
+ for (i = 0; pic32mx_devs[i].name; i++) {
if (pic32mx_devs[i].devid == (device_id & 0x0fffffff)) {
- printed = snprintf(buf, buf_size, "PIC32MX%s", pic32mx_devs[i].name);
+ command_print_sameline(cmd, "PIC32MX%s", pic32mx_devs[i].name);
break;
}
}
- if (pic32mx_devs[i].name == NULL)
- printed = snprintf(buf, buf_size, "Unknown");
+ if (!pic32mx_devs[i].name)
+ command_print_sameline(cmd, "Unknown");
- buf += printed;
- buf_size -= printed;
- snprintf(buf, buf_size, " Ver: 0x%02x",
+ command_print_sameline(cmd, " Ver: 0x%02x",
(unsigned)((device_id >> 28) & 0xf));
return ERROR_OK;
struct flash_bank *bank;
int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 2, &bank);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
if (address < bank->base || address >= (bank->base + bank->size)) {
- command_print(CMD_CTX, "flash address '%s' is out of bounds", CMD_ARGV[0]);
+ command_print(CMD, "flash address '%s' is out of bounds", CMD_ARGV[0]);
return ERROR_OK;
}
res = ERROR_FLASH_OPERATION_FAILED;
if (res == ERROR_OK)
- command_print(CMD_CTX, "pic32mx pgm word complete");
+ command_print(CMD, "pic32mx pgm word complete");
else
- command_print(CMD_CTX, "pic32mx pgm word failed (status = 0x%x)", status);
+ command_print(CMD, "pic32mx pgm word failed (status = 0x%x)", status);
return ERROR_OK;
}
COMMAND_HANDLER(pic32mx_handle_unlock_command)
{
- uint32_t mchip_cmd;
struct target *target = NULL;
struct mips_m4k_common *mips_m4k;
struct mips_ejtag *ejtag_info;
int timeout = 10;
if (CMD_ARGC < 1) {
- command_print(CMD_CTX, "pic32mx unlock <bank>");
+ command_print(CMD, "pic32mx unlock <bank>");
return ERROR_COMMAND_SYNTAX_ERROR;
}
struct flash_bank *bank;
int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
target = bank->target;
mips_ejtag_set_instr(ejtag_info, MTAP_COMMAND);
/* first check status of device */
- mchip_cmd = MCHP_STATUS;
+ uint8_t mchip_cmd = MCHP_STATUS;
mips_ejtag_drscan_8(ejtag_info, &mchip_cmd);
if (mchip_cmd & (1 << 7)) {
/* device is not locked */
- command_print(CMD_CTX, "pic32mx is already unlocked, erasing anyway");
+ command_print(CMD, "pic32mx is already unlocked, erasing anyway");
}
/* unlock/erase device */
mchip_cmd = MCHP_STATUS;
mips_ejtag_drscan_8(ejtag_info, &mchip_cmd);
if (timeout-- == 0) {
- LOG_DEBUG("timeout waiting for unlock: 0x%" PRIx32 "", mchip_cmd);
+ LOG_DEBUG("timeout waiting for unlock: 0x%" PRIx8 "", mchip_cmd);
break;
}
alive_sleep(1);
/* select ejtag tap */
mips_ejtag_set_instr(ejtag_info, MTAP_SW_ETAP);
- command_print(CMD_CTX, "pic32mx unlocked.\n"
+ command_print(CMD, "pic32mx unlocked.\n"
"INFO: a reset or power cycle is required "
"for the new settings to take effect.");
COMMAND_REGISTRATION_DONE
};
-struct flash_driver pic32mx_flash = {
+const struct flash_driver pic32mx_flash = {
.name = "pic32mx",
.commands = pic32mx_command_handlers,
.flash_bank_command = pic32mx_flash_bank_command,
.erase_check = default_flash_blank_check,
.protect_check = pic32mx_protect_check,
.info = pic32mx_info,
+ .free_driver_priv = default_flash_free_driver_priv,
};
projects / fw / openocd / blobdiff