+// SPDX-License-Identifier: GPL-2.0-or-later
+
/***************************************************************************
* Copyright (C) 2005 by Dominic Rath *
* Dominic.Rath@gmx.de *
* *
* Copyright (C) 2008 by John McCarthy *
* jgmcc@magma.ca *
- * *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
***************************************************************************/
+
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
+#include <jtag/jtag.h>
#include "imp.h"
#include <target/algorithm.h>
#include <target/mips32.h>
* Note: These macros only work for KSEG0/KSEG1 addresses.
*/
-#define Virt2Phys(v) ((v) & 0x1FFFFFFF)
+#define virt2phys(v) ((v) & 0x1FFFFFFF)
/* pic32mx configuration register locations */
+#define PIC32MX_DEVCFG0_1XX_2XX 0xBFC00BFC
#define PIC32MX_DEVCFG0 0xBFC02FFC
#define PIC32MX_DEVCFG1 0xBFC02FF8
#define PIC32MX_DEVCFG2 0xBFC02FF4
#define NVMKEY1 0xAA996655
#define NVMKEY2 0x556699AA
-struct pic32mx_flash_bank
-{
- struct working_area *write_algorithm;
- int probed;
+#define MX_1XX_2XX 1 /* PIC32mx1xx/2xx */
+#define MX_17X_27X 2 /* PIC32mx17x/27x */
+
+struct pic32mx_flash_bank {
+ bool probed;
+ int dev_type; /* Default 0. 1 for Pic32MX1XX/2XX variant */
};
/*
- * DEVID values as per PIC32MX Flash Programming Specification Rev H
+ * DEVID values as per PIC32MX Flash Programming Specification Rev N
*/
static const struct pic32mx_devs_s {
{0x04A06053, "120F032B"},
{0x04A08053, "120F032C"},
{0x04A0A053, "120F032D"},
+ {0x04D07053, "130F064B"},
+ {0x04D09053, "130F064C"},
+ {0x04D0B053, "130F064D"},
+ {0x04D06053, "150F128B"},
+ {0x04D08053, "150F128C"},
+ {0x04D0A053, "150F128D"},
+ {0x06610053, "170F256B"},
+ {0x0661A053, "170F256D"},
{0x04A01053, "210F016B"},
{0x04A03053, "210F016C"},
{0x04A05053, "210F016D"},
{0x04A00053, "220F032B"},
{0x04A02053, "220F032C"},
{0x04A04053, "220F032D"},
+ {0x04D01053, "230F064B"},
+ {0x04D03053, "230F064C"},
+ {0x04D05053, "230F064D"},
+ {0x04D00053, "250F128B"},
+ {0x04D02053, "250F128C"},
+ {0x04D04053, "250F128D"},
+ {0x06600053, "270F256B"},
+ {0x0660A053, "270F256D"},
+ {0x05600053, "330F064H"},
+ {0x05601053, "330F064L"},
+ {0x05602053, "430F064H"},
+ {0x05603053, "430F064L"},
+ {0x0570C053, "350F128H"},
+ {0x0570D053, "350F128L"},
+ {0x0570E053, "450F128H"},
+ {0x0570F053, "450F128L"},
+ {0x05704053, "350F256H"},
+ {0x05705053, "350F256L"},
+ {0x05706053, "450F256H"},
+ {0x05707053, "450F256L"},
+ {0x05808053, "370F512H"},
+ {0x05809053, "370F512L"},
+ {0x0580A053, "470F512H"},
+ {0x0580B053, "470F512L"},
{0x00938053, "360F512L"},
{0x00934053, "360F256L"},
{0x0092D053, "340F128L"},
struct pic32mx_flash_bank *pic32mx_info;
if (CMD_ARGC < 6)
- {
- LOG_WARNING("incomplete flash_bank pic32mx configuration");
- return ERROR_FLASH_BANK_INVALID;
- }
+ return ERROR_COMMAND_SYNTAX_ERROR;
pic32mx_info = malloc(sizeof(struct pic32mx_flash_bank));
bank->driver_priv = pic32mx_info;
- pic32mx_info->write_algorithm = NULL;
- pic32mx_info->probed = 0;
+ pic32mx_info->probed = false;
+ pic32mx_info->dev_type = 0;
return ERROR_OK;
}
uint32_t status;
/* wait for busy to clear */
- while (((status = pic32mx_get_flash_status(bank)) & NVMCON_NVMWR) && (timeout-- > 0))
- {
+ while (((status = pic32mx_get_flash_status(bank)) & NVMCON_NVMWR) && (timeout-- > 0)) {
LOG_DEBUG("status: 0x%" PRIx32, status);
alive_sleep(1);
}
static int pic32mx_protect_check(struct flash_bank *bank)
{
struct target *target = bank->target;
+ struct pic32mx_flash_bank *pic32mx_info = bank->driver_priv;
+ uint32_t config0_address;
uint32_t devcfg0;
- int s;
- int num_pages;
+ unsigned int s, num_pages;
- if (target->state != TARGET_HALTED)
- {
+ if (target->state != TARGET_HALTED) {
LOG_ERROR("Target not halted");
return ERROR_TARGET_NOT_HALTED;
}
- target_read_u32(target, PIC32MX_DEVCFG0, &devcfg0);
+ switch (pic32mx_info->dev_type) {
+ case MX_1XX_2XX:
+ case MX_17X_27X:
+ config0_address = PIC32MX_DEVCFG0_1XX_2XX;
+ break;
+ default:
+ config0_address = PIC32MX_DEVCFG0;
+ break;
+ }
+
+ target_read_u32(target, config0_address, &devcfg0);
if ((devcfg0 & (1 << 28)) == 0) /* code protect bit */
- num_pages = 0xffff; /* All pages protected */
- else if (Virt2Phys(bank->base) == PIC32MX_PHYS_BOOT_FLASH)
- {
+ num_pages = 0xffff; /* All pages protected */
+ else if (virt2phys(bank->base) == PIC32MX_PHYS_BOOT_FLASH) {
if (devcfg0 & (1 << 24))
- num_pages = 0; /* All pages unprotected */
+ num_pages = 0; /* All pages unprotected */
else
- num_pages = 0xffff; /* All pages protected */
+ num_pages = 0xffff; /* All pages protected */
+ } else {
+ /* pgm flash */
+ switch (pic32mx_info->dev_type) {
+ case MX_1XX_2XX:
+ num_pages = (~devcfg0 >> 10) & 0x7f;
+ break;
+ case MX_17X_27X:
+ num_pages = (~devcfg0 >> 10) & 0x1ff;
+ break;
+ default:
+ num_pages = (~devcfg0 >> 12) & 0xff;
+ break;
+ }
}
- else /* pgm flash */
- num_pages = (~devcfg0 >> 12) & 0xff;
for (s = 0; s < bank->num_sectors && s < num_pages; s++)
bank->sectors[s].is_protected = 1;
return ERROR_OK;
}
-static int pic32mx_erase(struct flash_bank *bank, int first, int last)
+static int pic32mx_erase(struct flash_bank *bank, unsigned int first,
+ unsigned int last)
{
struct target *target = bank->target;
- int i;
uint32_t status;
- if (bank->target->state != TARGET_HALTED)
- {
+ if (bank->target->state != TARGET_HALTED) {
LOG_ERROR("Target not halted");
return ERROR_TARGET_NOT_HALTED;
}
if ((first == 0) && (last == (bank->num_sectors - 1))
- && (Virt2Phys(bank->base) == PIC32MX_PHYS_PGM_FLASH))
- {
+ && (virt2phys(bank->base) == PIC32MX_PHYS_PGM_FLASH)) {
/* this will only erase the Program Flash (PFM), not the Boot Flash (BFM)
* we need to use the MTAP to perform a full erase */
LOG_DEBUG("Erasing entire program flash");
return ERROR_OK;
}
- for (i = first; i <= last; i++)
- {
- target_write_u32(target, PIC32MX_NVMADDR, Virt2Phys(bank->base + bank->sectors[i].offset));
+ for (unsigned int i = first; i <= last; i++) {
+ target_write_u32(target, PIC32MX_NVMADDR, virt2phys(bank->base + bank->sectors[i].offset));
status = pic32mx_nvm_exec(bank, NVMCON_OP_PAGE_ERASE, 10);
return ERROR_FLASH_OPERATION_FAILED;
if (status & NVMCON_LVDERR)
return ERROR_FLASH_OPERATION_FAILED;
- bank->sectors[i].is_erased = 1;
}
return ERROR_OK;
}
-static int pic32mx_protect(struct flash_bank *bank, int set, int first, int last)
+static int pic32mx_protect(struct flash_bank *bank, int set, unsigned int first,
+ unsigned int last)
{
struct target *target = bank->target;
- if (target->state != TARGET_HALTED)
- {
+ if (target->state != TARGET_HALTED) {
LOG_ERROR("Target not halted");
return ERROR_TARGET_NOT_HALTED;
}
return ERROR_OK;
}
-/* see contib/loaders/flash/pic32mx.s for src */
+/* see contrib/loaders/flash/pic32mx.s for src */
-static const uint32_t pic32mx_flash_write_code[] = {
+static uint32_t pic32mx_flash_write_code[] = {
/* write: */
0x3C08AA99, /* lui $t0, 0xaa99 */
0x35086655, /* ori $t0, 0x6655 */
0x1600FFFD, /* bne $s0, $zero, waitflash */
0x00000000, /* nop */
0x00000000, /* nop */
- 0x00000000, /* nop */
+ 0x00000000, /* nop */
0x00000000, /* nop */
0x00000000, /* nop */
0x8D510000, /* lw $s1, 0($t2) */
0x00000000 /* nop */
};
-static int pic32mx_write_block(struct flash_bank *bank, uint8_t *buffer,
+static int pic32mx_write_block(struct flash_bank *bank, const uint8_t *buffer,
uint32_t offset, uint32_t count)
{
struct target *target = bank->target;
uint32_t buffer_size = 16384;
+ struct working_area *write_algorithm;
struct working_area *source;
uint32_t address = bank->base + offset;
struct reg_param reg_params[3];
+ uint32_t row_size;
int retval = ERROR_OK;
struct pic32mx_flash_bank *pic32mx_info = bank->driver_priv;
/* flash write code */
if (target_alloc_working_area(target, sizeof(pic32mx_flash_write_code),
- &pic32mx_info->write_algorithm) != ERROR_OK)
- {
+ &write_algorithm) != ERROR_OK) {
LOG_WARNING("no working area available, can't do block memory writes");
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
- };
+ }
+
+ /* Change values for counters and row size, depending on variant */
+ switch (pic32mx_info->dev_type) {
+ case MX_1XX_2XX:
+ case MX_17X_27X:
+ /* 128 byte row */
+ pic32mx_flash_write_code[8] = 0x2CD30020;
+ pic32mx_flash_write_code[14] = 0x24840080;
+ pic32mx_flash_write_code[15] = 0x24A50080;
+ pic32mx_flash_write_code[17] = 0x24C6FFE0;
+ row_size = 128;
+ break;
+ default:
+ /* 512 byte row */
+ pic32mx_flash_write_code[8] = 0x2CD30080;
+ pic32mx_flash_write_code[14] = 0x24840200;
+ pic32mx_flash_write_code[15] = 0x24A50200;
+ pic32mx_flash_write_code[17] = 0x24C6FF80;
+ row_size = 512;
+ break;
+ }
- if ((retval = target_write_buffer(target,
- pic32mx_info->write_algorithm->address,
- sizeof(pic32mx_flash_write_code),
- (uint8_t*)pic32mx_flash_write_code)) != ERROR_OK)
+ uint8_t code[sizeof(pic32mx_flash_write_code)];
+ target_buffer_set_u32_array(target, code, ARRAY_SIZE(pic32mx_flash_write_code),
+ pic32mx_flash_write_code);
+ retval = target_write_buffer(target, write_algorithm->address, sizeof(code), code);
+ if (retval != ERROR_OK)
return retval;
/* memory buffer */
- while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK)
- {
+ while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK) {
buffer_size /= 2;
- if (buffer_size <= 256)
- {
- /* if we already allocated the writing code, but failed to get a
+ if (buffer_size <= 256) {
+ /* we already allocated the writing code, but failed to get a
* buffer, free the algorithm */
- if (pic32mx_info->write_algorithm)
- target_free_working_area(target, pic32mx_info->write_algorithm);
+ target_free_working_area(target, write_algorithm);
LOG_WARNING("no large enough working area available, can't do block memory writes");
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
- };
+ }
mips32_info.common_magic = MIPS32_COMMON_MAGIC;
mips32_info.isa_mode = MIPS32_ISA_MIPS32;
- init_reg_param(®_params[0], "a0", 32, PARAM_IN_OUT);
- init_reg_param(®_params[1], "a1", 32, PARAM_OUT);
- init_reg_param(®_params[2], "a2", 32, PARAM_OUT);
+ init_reg_param(®_params[0], "r4", 32, PARAM_IN_OUT);
+ init_reg_param(®_params[1], "r5", 32, PARAM_OUT);
+ init_reg_param(®_params[2], "r6", 32, PARAM_OUT);
+
+ int row_offset = offset % row_size;
+ uint8_t *new_buffer = NULL;
+ if (row_offset && (count >= (row_size / 4))) {
+ new_buffer = malloc(buffer_size);
+ if (!new_buffer) {
+ LOG_ERROR("Out of memory");
+ return ERROR_FAIL;
+ }
+ memset(new_buffer, 0xff, row_offset);
+ address -= row_offset;
+ } else
+ row_offset = 0;
- while (count > 0)
- {
+ while (count > 0) {
uint32_t status;
- uint32_t thisrun_count = (count > (buffer_size / 4)) ?
- (buffer_size / 4) : count;
-
- if ((retval = target_write_buffer(target, source->address,
- thisrun_count * 4, buffer)) != ERROR_OK)
- break;
+ uint32_t thisrun_count;
+
+ if (row_offset) {
+ thisrun_count = (count > ((buffer_size - row_offset) / 4)) ?
+ ((buffer_size - row_offset) / 4) : count;
+
+ memcpy(new_buffer + row_offset, buffer, thisrun_count * 4);
+
+ retval = target_write_buffer(target, source->address,
+ row_offset + thisrun_count * 4, new_buffer);
+ if (retval != ERROR_OK)
+ break;
+ } else {
+ thisrun_count = (count > (buffer_size / 4)) ?
+ (buffer_size / 4) : count;
+
+ retval = target_write_buffer(target, source->address,
+ thisrun_count * 4, buffer);
+ if (retval != ERROR_OK)
+ break;
+ }
- buf_set_u32(reg_params[0].value, 0, 32, Virt2Phys(source->address));
- buf_set_u32(reg_params[1].value, 0, 32, Virt2Phys(address));
- buf_set_u32(reg_params[2].value, 0, 32, thisrun_count);
+ buf_set_u32(reg_params[0].value, 0, 32, virt2phys(source->address));
+ buf_set_u32(reg_params[1].value, 0, 32, virt2phys(address));
+ buf_set_u32(reg_params[2].value, 0, 32, thisrun_count + row_offset / 4);
- if ((retval = target_run_algorithm(target, 0, NULL, 3, reg_params,
- pic32mx_info->write_algorithm->address,
- 0,
- 10000, &mips32_info)) != ERROR_OK)
- {
+ retval = target_run_algorithm(target, 0, NULL, 3, reg_params,
+ write_algorithm->address,
+ 0, 10000, &mips32_info);
+ if (retval != ERROR_OK) {
LOG_ERROR("error executing pic32mx flash write algorithm");
retval = ERROR_FLASH_OPERATION_FAILED;
break;
status = buf_get_u32(reg_params[0].value, 0, 32);
- if (status & NVMCON_NVMERR)
- {
+ if (status & NVMCON_NVMERR) {
LOG_ERROR("Flash write error NVMERR (status = 0x%08" PRIx32 ")", status);
retval = ERROR_FLASH_OPERATION_FAILED;
break;
}
- if (status & NVMCON_LVDERR)
- {
+ if (status & NVMCON_LVDERR) {
LOG_ERROR("Flash write error LVDERR (status = 0x%08" PRIx32 ")", status);
retval = ERROR_FLASH_OPERATION_FAILED;
break;
buffer += thisrun_count * 4;
address += thisrun_count * 4;
count -= thisrun_count;
+ if (row_offset) {
+ address += row_offset;
+ row_offset = 0;
+ }
}
target_free_working_area(target, source);
- target_free_working_area(target, pic32mx_info->write_algorithm);
+ target_free_working_area(target, write_algorithm);
destroy_reg_param(®_params[0]);
destroy_reg_param(®_params[1]);
destroy_reg_param(®_params[2]);
+ free(new_buffer);
return retval;
}
{
struct target *target = bank->target;
- target_write_u32(target, PIC32MX_NVMADDR, Virt2Phys(address));
+ target_write_u32(target, PIC32MX_NVMADDR, virt2phys(address));
target_write_u32(target, PIC32MX_NVMDATA, word);
return pic32mx_nvm_exec(bank, NVMCON_OP_WORD_PROG, 5);
}
-static int pic32mx_write(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
+static int pic32mx_write(struct flash_bank *bank, const uint8_t *buffer, uint32_t offset, uint32_t count)
{
uint32_t words_remaining = (count / 4);
uint32_t bytes_remaining = (count & 0x00000003);
uint32_t status;
int retval;
- if (bank->target->state != TARGET_HALTED)
- {
+ if (bank->target->state != TARGET_HALTED) {
LOG_ERROR("Target not halted");
return ERROR_TARGET_NOT_HALTED;
}
- LOG_DEBUG("writing to flash at address 0x%08" PRIx32 " at offset 0x%8.8" PRIx32
+ LOG_DEBUG("writing to flash at address " TARGET_ADDR_FMT " at offset 0x%8.8" PRIx32
" count: 0x%8.8" PRIx32 "", bank->base, offset, count);
- if (offset & 0x3)
- {
+ if (offset & 0x3) {
LOG_WARNING("offset 0x%" PRIx32 "breaks required 4-byte alignment", offset);
return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
}
/* multiple words (4-byte) to be programmed? */
- if (words_remaining > 0)
- {
+ if (words_remaining > 0) {
/* try using a block write */
- if ((retval = pic32mx_write_block(bank, buffer, offset, words_remaining)) != ERROR_OK)
- {
- if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
- {
+ retval = pic32mx_write_block(bank, buffer, offset, words_remaining);
+ if (retval != ERROR_OK) {
+ if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
/* if block write failed (no sufficient working area),
* we use normal (slow) single dword accesses */
LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
- }
- else if (retval == ERROR_FLASH_OPERATION_FAILED)
- {
+ } else if (retval == ERROR_FLASH_OPERATION_FAILED) {
LOG_ERROR("flash writing failed");
return retval;
}
- }
- else
- {
+ } else {
buffer += words_remaining * 4;
address += words_remaining * 4;
words_remaining = 0;
}
}
- while (words_remaining > 0)
- {
+ while (words_remaining > 0) {
uint32_t value;
memcpy(&value, buffer + bytes_written, sizeof(uint32_t));
status = pic32mx_write_word(bank, address, value);
- if (status & NVMCON_NVMERR)
- {
+ if (status & NVMCON_NVMERR) {
LOG_ERROR("Flash write error NVMERR (status = 0x%08" PRIx32 ")", status);
return ERROR_FLASH_OPERATION_FAILED;
}
- if (status & NVMCON_LVDERR)
- {
+ if (status & NVMCON_LVDERR) {
LOG_ERROR("Flash write error LVDERR (status = 0x%08" PRIx32 ")", status);
return ERROR_FLASH_OPERATION_FAILED;
}
address += 4;
}
- if (bytes_remaining)
- {
+ if (bytes_remaining) {
uint32_t value = 0xffffffff;
memcpy(&value, buffer + bytes_written, bytes_remaining);
status = pic32mx_write_word(bank, address, value);
- if (status & NVMCON_NVMERR)
- {
+ if (status & NVMCON_NVMERR) {
LOG_ERROR("Flash write error NVMERR (status = 0x%08" PRIx32 ")", status);
return ERROR_FLASH_OPERATION_FAILED;
}
- if (status & NVMCON_LVDERR)
- {
+ if (status & NVMCON_LVDERR) {
LOG_ERROR("Flash write error LVDERR (status = 0x%08" PRIx32 ")", status);
return ERROR_FLASH_OPERATION_FAILED;
}
uint32_t device_id;
int page_size;
- pic32mx_info->probed = 0;
+ pic32mx_info->probed = false;
device_id = ejtag_info->idcode;
LOG_INFO("device id = 0x%08" PRIx32 " (manuf 0x%03x dev 0x%04x, ver 0x%02x)",
return ERROR_FLASH_OPERATION_FAILED;
}
- page_size = 4096;
+ /* Check for PIC32mx1xx/2xx */
+ for (i = 0; pic32mx_devs[i].name; i++) {
+ if (pic32mx_devs[i].devid == (device_id & 0x0fffffff)) {
+ if ((pic32mx_devs[i].name[0] == '1') || (pic32mx_devs[i].name[0] == '2'))
+ pic32mx_info->dev_type = (pic32mx_devs[i].name[1] == '7') ? MX_17X_27X : MX_1XX_2XX;
+ break;
+ }
+ }
+
+ switch (pic32mx_info->dev_type) {
+ case MX_1XX_2XX:
+ case MX_17X_27X:
+ page_size = 1024;
+ break;
+ default:
+ page_size = 4096;
+ break;
+ }
- if (Virt2Phys(bank->base) == PIC32MX_PHYS_BOOT_FLASH)
- {
+ if (virt2phys(bank->base) == PIC32MX_PHYS_BOOT_FLASH) {
/* 0x1FC00000: Boot flash size */
#if 0
/* for some reason this register returns 8k for the boot bank size
}
#else
/* fixed 12k boot bank - see comments above */
- num_pages = (12 * 1024);
+ switch (pic32mx_info->dev_type) {
+ case MX_1XX_2XX:
+ case MX_17X_27X:
+ num_pages = (3 * 1024);
+ break;
+ default:
+ num_pages = (12 * 1024);
+ break;
+ }
#endif
- }
- else
- {
+ } else {
/* read the flash size from the device */
if (target_read_u32(target, PIC32MX_BMXPFMSZ, &num_pages) != ERROR_OK) {
- LOG_WARNING("PIC32MX flash size failed, probe inaccurate - assuming 512k flash");
- num_pages = (512 * 1024);
+ switch (pic32mx_info->dev_type) {
+ case MX_1XX_2XX:
+ case MX_17X_27X:
+ LOG_WARNING("PIC32MX flash size failed, probe inaccurate - assuming 32k flash");
+ num_pages = (32 * 1024);
+ break;
+ default:
+ LOG_WARNING("PIC32MX flash size failed, probe inaccurate - assuming 512k flash");
+ num_pages = (512 * 1024);
+ break;
+ }
}
}
- LOG_INFO("flash size = %" PRId32 "kbytes", num_pages / 1024);
+ LOG_INFO("flash size = %" PRIu32 " KiB", num_pages / 1024);
- if (bank->sectors)
- {
- free(bank->sectors);
- bank->sectors = NULL;
- }
+ free(bank->sectors);
/* calculate numbers of pages */
num_pages /= page_size;
bank->num_sectors = num_pages;
bank->sectors = malloc(sizeof(struct flash_sector) * num_pages);
- for (i = 0; i < (int)num_pages; i++)
- {
+ for (i = 0; i < (int)num_pages; i++) {
bank->sectors[i].offset = i * page_size;
bank->sectors[i].size = page_size;
bank->sectors[i].is_erased = -1;
bank->sectors[i].is_protected = 1;
}
- pic32mx_info->probed = 1;
+ pic32mx_info->probed = true;
return ERROR_OK;
}
return pic32mx_probe(bank);
}
-static int pic32mx_info(struct flash_bank *bank, char *buf, int buf_size)
+static int pic32mx_info(struct flash_bank *bank, struct command_invocation *cmd)
{
struct target *target = bank->target;
struct mips32_common *mips32 = target->arch_info;
struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
uint32_t device_id;
- int printed = 0, i;
device_id = ejtag_info->idcode;
if (((device_id >> 1) & 0x7ff) != PIC32MX_MANUF_ID) {
- snprintf(buf, buf_size,
- "Cannot identify target as a PIC32MX family (manufacturer 0x%03d != 0x%03d)\n",
- (unsigned)((device_id >> 1) & 0x7ff),
- PIC32MX_MANUF_ID);
+ command_print_sameline(cmd,
+ "Cannot identify target as a PIC32MX family (manufacturer 0x%03x != 0x%03x)\n",
+ (unsigned)((device_id >> 1) & 0x7ff),
+ PIC32MX_MANUF_ID);
return ERROR_FLASH_OPERATION_FAILED;
}
- for (i = 0; pic32mx_devs[i].name != NULL; i++)
- {
+ int i;
+ for (i = 0; pic32mx_devs[i].name; i++) {
if (pic32mx_devs[i].devid == (device_id & 0x0fffffff)) {
- printed = snprintf(buf, buf_size, "PIC32MX%s", pic32mx_devs[i].name);
+ command_print_sameline(cmd, "PIC32MX%s", pic32mx_devs[i].name);
break;
}
}
- if (pic32mx_devs[i].name == NULL) {
- printed = snprintf(buf, buf_size, "Unknown");
- }
+ if (!pic32mx_devs[i].name)
+ command_print_sameline(cmd, "Unknown");
- buf += printed;
- buf_size -= printed;
- printed = snprintf(buf, buf_size, " Ver: 0x%02x",
+ command_print_sameline(cmd, " Ver: 0x%02x",
(unsigned)((device_id >> 28) & 0xf));
return ERROR_OK;
int status, res;
if (CMD_ARGC != 3)
- {
- command_print(CMD_CTX, "pic32mx pgm_word <addr> <value> <bank>");
- return ERROR_OK;
- }
+ return ERROR_COMMAND_SYNTAX_ERROR;
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], address);
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value);
struct flash_bank *bank;
int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 2, &bank);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
- if (address < bank->base || address >= (bank->base + bank->size))
- {
- command_print(CMD_CTX, "flash address '%s' is out of bounds", CMD_ARGV[0]);
+ if (address < bank->base || address >= (bank->base + bank->size)) {
+ command_print(CMD, "flash address '%s' is out of bounds", CMD_ARGV[0]);
return ERROR_OK;
}
res = ERROR_FLASH_OPERATION_FAILED;
if (res == ERROR_OK)
- command_print(CMD_CTX, "pic32mx pgm word complete");
+ command_print(CMD, "pic32mx pgm word complete");
else
- command_print(CMD_CTX, "pic32mx pgm word failed (status = 0x%x)", status);
+ command_print(CMD, "pic32mx pgm word failed (status = 0x%x)", status);
return ERROR_OK;
}
COMMAND_HANDLER(pic32mx_handle_unlock_command)
{
- uint32_t mchip_cmd;
struct target *target = NULL;
struct mips_m4k_common *mips_m4k;
struct mips_ejtag *ejtag_info;
int timeout = 10;
- if (CMD_ARGC < 1)
- {
- command_print(CMD_CTX, "pic32mx unlock <bank>");
- return ERROR_OK;
+ if (CMD_ARGC < 1) {
+ command_print(CMD, "pic32mx unlock <bank>");
+ return ERROR_COMMAND_SYNTAX_ERROR;
}
struct flash_bank *bank;
int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
target = bank->target;
mips_ejtag_set_instr(ejtag_info, MTAP_COMMAND);
/* first check status of device */
- mchip_cmd = MCHP_STATUS;
+ uint8_t mchip_cmd = MCHP_STATUS;
mips_ejtag_drscan_8(ejtag_info, &mchip_cmd);
- if (mchip_cmd & (1 << 7))
- {
+ if (mchip_cmd & (1 << 7)) {
/* device is not locked */
- command_print(CMD_CTX, "pic32mx is already unlocked, erasing anyway");
+ command_print(CMD, "pic32mx is already unlocked, erasing anyway");
}
/* unlock/erase device */
mips_ejtag_drscan_8_out(ejtag_info, MCHP_ASERT_RST);
+ jtag_add_sleep(200);
mips_ejtag_drscan_8_out(ejtag_info, MCHP_ERASE);
do {
mchip_cmd = MCHP_STATUS;
mips_ejtag_drscan_8(ejtag_info, &mchip_cmd);
- if (timeout-- == 0)
- {
- LOG_DEBUG("timeout waiting for unlock: 0x%" PRIx32 "", mchip_cmd);
+ if (timeout-- == 0) {
+ LOG_DEBUG("timeout waiting for unlock: 0x%" PRIx8 "", mchip_cmd);
break;
}
alive_sleep(1);
/* select ejtag tap */
mips_ejtag_set_instr(ejtag_info, MTAP_SW_ETAP);
- command_print(CMD_CTX, "pic32mx unlocked.\n"
+ command_print(CMD, "pic32mx unlocked.\n"
"INFO: a reset or power cycle is required "
"for the new settings to take effect.");
static const struct command_registration pic32mx_exec_command_handlers[] = {
{
.name = "pgm_word",
+ .usage = "<addr> <value> <bank>",
.handler = pic32mx_handle_pgm_word_command,
.mode = COMMAND_EXEC,
.help = "program a word",
.name = "pic32mx",
.mode = COMMAND_ANY,
.help = "pic32mx flash command group",
+ .usage = "",
.chain = pic32mx_exec_command_handlers,
},
COMMAND_REGISTRATION_DONE
};
-struct flash_driver pic32mx_flash = {
+const struct flash_driver pic32mx_flash = {
.name = "pic32mx",
.commands = pic32mx_command_handlers,
.flash_bank_command = pic32mx_flash_bank_command,
.read = default_flash_read,
.probe = pic32mx_probe,
.auto_probe = pic32mx_auto_probe,
- .erase_check = default_flash_mem_blank_check,
+ .erase_check = default_flash_blank_check,
.protect_check = pic32mx_protect_check,
.info = pic32mx_info,
+ .free_driver_priv = default_flash_free_driver_priv,
};
projects / fw / openocd / blobdiff