* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
+ * along with this program. If not, see <http://www.gnu.org/licenses/>. *
***************************************************************************/
#ifdef HAVE_CONFIG_H
/* pic32mx configuration register locations */
-#define PIC32MX_DEVCFG0_1_2 0xBFC00BFC
+#define PIC32MX_DEVCFG0_1xx_2xx 0xBFC00BFC
#define PIC32MX_DEVCFG0 0xBFC02FFC
#define PIC32MX_DEVCFG1 0xBFC02FF8
#define PIC32MX_DEVCFG2 0xBFC02FF4
#define NVMKEY1 0xAA996655
#define NVMKEY2 0x556699AA
-#define MX_1_2 1 /* PIC32mx1xx/2xx */
+#define MX_1xx_2xx 1 /* PIC32mx1xx/2xx */
+#define MX_17x_27x 2 /* PIC32mx17x/27x */
struct pic32mx_flash_bank {
- int probed;
+ bool probed;
int dev_type; /* Default 0. 1 for Pic32MX1XX/2XX variant */
};
/*
- * DEVID values as per PIC32MX Flash Programming Specification Rev J
+ * DEVID values as per PIC32MX Flash Programming Specification Rev N
*/
static const struct pic32mx_devs_s {
{0x04D06053, "150F128B"},
{0x04D08053, "150F128C"},
{0x04D0A053, "150F128D"},
+ {0x06610053, "170F256B"},
+ {0x0661A053, "170F256D"},
{0x04A01053, "210F016B"},
{0x04A03053, "210F016C"},
{0x04A05053, "210F016D"},
{0x04D00053, "250F128B"},
{0x04D02053, "250F128C"},
{0x04D04053, "250F128D"},
+ {0x06600053, "270F256B"},
+ {0x0660A053, "270F256D"},
+ {0x05600053, "330F064H"},
+ {0x05601053, "330F064L"},
+ {0x05602053, "430F064H"},
+ {0x05603053, "430F064L"},
+ {0x0570C053, "350F128H"},
+ {0x0570D053, "350F128L"},
+ {0x0570E053, "450F128H"},
+ {0x0570F053, "450F128L"},
+ {0x05704053, "350F256H"},
+ {0x05705053, "350F256L"},
+ {0x05706053, "450F256H"},
+ {0x05707053, "450F256L"},
+ {0x05808053, "370F512H"},
+ {0x05809053, "370F512L"},
+ {0x0580A053, "470F512H"},
+ {0x0580B053, "470F512L"},
{0x00938053, "360F512L"},
{0x00934053, "360F256L"},
{0x0092D053, "340F128L"},
pic32mx_info = malloc(sizeof(struct pic32mx_flash_bank));
bank->driver_priv = pic32mx_info;
- pic32mx_info->probed = 0;
+ pic32mx_info->probed = false;
pic32mx_info->dev_type = 0;
return ERROR_OK;
uint32_t config0_address;
uint32_t devcfg0;
- int s;
- int num_pages;
+ unsigned int s, num_pages;
if (target->state != TARGET_HALTED) {
LOG_ERROR("Target not halted");
return ERROR_TARGET_NOT_HALTED;
}
- if (pic32mx_info->dev_type == MX_1_2)
- config0_address = PIC32MX_DEVCFG0_1_2;
- else
+ switch (pic32mx_info->dev_type) {
+ case MX_1xx_2xx:
+ case MX_17x_27x:
+ config0_address = PIC32MX_DEVCFG0_1xx_2xx;
+ break;
+ default:
config0_address = PIC32MX_DEVCFG0;
+ break;
+ }
target_read_u32(target, config0_address, &devcfg0);
num_pages = 0xffff; /* All pages protected */
} else {
/* pgm flash */
- if (pic32mx_info->dev_type == MX_1_2)
- num_pages = (~devcfg0 >> 10) & 0x3f;
- else
+ switch (pic32mx_info->dev_type) {
+ case MX_1xx_2xx:
+ num_pages = (~devcfg0 >> 10) & 0x7f;
+ break;
+ case MX_17x_27x:
+ num_pages = (~devcfg0 >> 10) & 0x1ff;
+ break;
+ default:
num_pages = (~devcfg0 >> 12) & 0xff;
+ break;
+ }
}
for (s = 0; s < bank->num_sectors && s < num_pages; s++)
return ERROR_OK;
}
-static int pic32mx_erase(struct flash_bank *bank, int first, int last)
+static int pic32mx_erase(struct flash_bank *bank, unsigned int first,
+ unsigned int last)
{
struct target *target = bank->target;
- int i;
uint32_t status;
if (bank->target->state != TARGET_HALTED) {
return ERROR_OK;
}
- for (i = first; i <= last; i++) {
+ for (unsigned int i = first; i <= last; i++) {
target_write_u32(target, PIC32MX_NVMADDR, Virt2Phys(bank->base + bank->sectors[i].offset));
status = pic32mx_nvm_exec(bank, NVMCON_OP_PAGE_ERASE, 10);
return ERROR_OK;
}
-static int pic32mx_protect(struct flash_bank *bank, int set, int first, int last)
+static int pic32mx_protect(struct flash_bank *bank, int set, unsigned int first,
+ unsigned int last)
{
struct target *target = bank->target;
&write_algorithm) != ERROR_OK) {
LOG_WARNING("no working area available, can't do block memory writes");
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
- };
+ }
/* Change values for counters and row size, depending on variant */
- if (pic32mx_info->dev_type == MX_1_2) {
+ switch (pic32mx_info->dev_type) {
+ case MX_1xx_2xx:
+ case MX_17x_27x:
/* 128 byte row */
pic32mx_flash_write_code[8] = 0x2CD30020;
pic32mx_flash_write_code[14] = 0x24840080;
pic32mx_flash_write_code[15] = 0x24A50080;
pic32mx_flash_write_code[17] = 0x24C6FFE0;
row_size = 128;
- } else {
+ break;
+ default:
/* 512 byte row */
pic32mx_flash_write_code[8] = 0x2CD30080;
pic32mx_flash_write_code[14] = 0x24840200;
pic32mx_flash_write_code[15] = 0x24A50200;
pic32mx_flash_write_code[17] = 0x24C6FF80;
row_size = 512;
+ break;
}
uint8_t code[sizeof(pic32mx_flash_write_code)];
mips32_info.common_magic = MIPS32_COMMON_MAGIC;
mips32_info.isa_mode = MIPS32_ISA_MIPS32;
- init_reg_param(®_params[0], "a0", 32, PARAM_IN_OUT);
- init_reg_param(®_params[1], "a1", 32, PARAM_OUT);
- init_reg_param(®_params[2], "a2", 32, PARAM_OUT);
+ init_reg_param(®_params[0], "r4", 32, PARAM_IN_OUT);
+ init_reg_param(®_params[1], "r5", 32, PARAM_OUT);
+ init_reg_param(®_params[2], "r6", 32, PARAM_OUT);
int row_offset = offset % row_size;
uint8_t *new_buffer = NULL;
return ERROR_TARGET_NOT_HALTED;
}
- LOG_DEBUG("writing to flash at address 0x%08" PRIx32 " at offset 0x%8.8" PRIx32
+ LOG_DEBUG("writing to flash at address " TARGET_ADDR_FMT " at offset 0x%8.8" PRIx32
" count: 0x%8.8" PRIx32 "", bank->base, offset, count);
if (offset & 0x3) {
uint32_t device_id;
int page_size;
- pic32mx_info->probed = 0;
+ pic32mx_info->probed = false;
device_id = ejtag_info->idcode;
LOG_INFO("device id = 0x%08" PRIx32 " (manuf 0x%03x dev 0x%04x, ver 0x%02x)",
/* Check for PIC32mx1xx/2xx */
for (i = 0; pic32mx_devs[i].name != NULL; i++) {
if (pic32mx_devs[i].devid == (device_id & 0x0fffffff)) {
- if ((*(pic32mx_devs[i].name) == '1') || (*(pic32mx_devs[i].name) == '2'))
- pic32mx_info->dev_type = MX_1_2;
+ if ((pic32mx_devs[i].name[0] == '1') || (pic32mx_devs[i].name[0] == '2'))
+ pic32mx_info->dev_type = (pic32mx_devs[i].name[1] == '7') ? MX_17x_27x : MX_1xx_2xx;
break;
}
}
- if (pic32mx_info->dev_type == MX_1_2)
+ switch (pic32mx_info->dev_type) {
+ case MX_1xx_2xx:
+ case MX_17x_27x:
page_size = 1024;
- else
+ break;
+ default:
page_size = 4096;
-
+ break;
+ }
if (Virt2Phys(bank->base) == PIC32MX_PHYS_BOOT_FLASH) {
/* 0x1FC00000: Boot flash size */
}
#else
/* fixed 12k boot bank - see comments above */
- if (pic32mx_info->dev_type == MX_1_2)
+ switch (pic32mx_info->dev_type) {
+ case MX_1xx_2xx:
+ case MX_17x_27x:
num_pages = (3 * 1024);
- else
+ break;
+ default:
num_pages = (12 * 1024);
+ break;
+ }
#endif
} else {
/* read the flash size from the device */
if (target_read_u32(target, PIC32MX_BMXPFMSZ, &num_pages) != ERROR_OK) {
- if (pic32mx_info->dev_type == MX_1_2) {
+ switch (pic32mx_info->dev_type) {
+ case MX_1xx_2xx:
+ case MX_17x_27x:
LOG_WARNING("PIC32MX flash size failed, probe inaccurate - assuming 32k flash");
num_pages = (32 * 1024);
- } else {
+ break;
+ default:
LOG_WARNING("PIC32MX flash size failed, probe inaccurate - assuming 512k flash");
num_pages = (512 * 1024);
+ break;
}
}
}
bank->sectors[i].is_protected = 1;
}
- pic32mx_info->probed = 1;
+ pic32mx_info->probed = true;
return ERROR_OK;
}
return retval;
if (address < bank->base || address >= (bank->base + bank->size)) {
- command_print(CMD_CTX, "flash address '%s' is out of bounds", CMD_ARGV[0]);
+ command_print(CMD, "flash address '%s' is out of bounds", CMD_ARGV[0]);
return ERROR_OK;
}
res = ERROR_FLASH_OPERATION_FAILED;
if (res == ERROR_OK)
- command_print(CMD_CTX, "pic32mx pgm word complete");
+ command_print(CMD, "pic32mx pgm word complete");
else
- command_print(CMD_CTX, "pic32mx pgm word failed (status = 0x%x)", status);
+ command_print(CMD, "pic32mx pgm word failed (status = 0x%x)", status);
return ERROR_OK;
}
COMMAND_HANDLER(pic32mx_handle_unlock_command)
{
- uint32_t mchip_cmd;
struct target *target = NULL;
struct mips_m4k_common *mips_m4k;
struct mips_ejtag *ejtag_info;
int timeout = 10;
if (CMD_ARGC < 1) {
- command_print(CMD_CTX, "pic32mx unlock <bank>");
+ command_print(CMD, "pic32mx unlock <bank>");
return ERROR_COMMAND_SYNTAX_ERROR;
}
mips_ejtag_set_instr(ejtag_info, MTAP_COMMAND);
/* first check status of device */
- mchip_cmd = MCHP_STATUS;
+ uint8_t mchip_cmd = MCHP_STATUS;
mips_ejtag_drscan_8(ejtag_info, &mchip_cmd);
if (mchip_cmd & (1 << 7)) {
/* device is not locked */
- command_print(CMD_CTX, "pic32mx is already unlocked, erasing anyway");
+ command_print(CMD, "pic32mx is already unlocked, erasing anyway");
}
/* unlock/erase device */
/* select ejtag tap */
mips_ejtag_set_instr(ejtag_info, MTAP_SW_ETAP);
- command_print(CMD_CTX, "pic32mx unlocked.\n"
+ command_print(CMD, "pic32mx unlocked.\n"
"INFO: a reset or power cycle is required "
"for the new settings to take effect.");
COMMAND_REGISTRATION_DONE
};
-struct flash_driver pic32mx_flash = {
+const struct flash_driver pic32mx_flash = {
.name = "pic32mx",
.commands = pic32mx_command_handlers,
.flash_bank_command = pic32mx_flash_bank_command,
.erase_check = default_flash_blank_check,
.protect_check = pic32mx_protect_check,
.info = pic32mx_info,
+ .free_driver_priv = default_flash_free_driver_priv,
};
projects / fw / openocd / blobdiff