/***************************************************************************
* Copyright (C) 2013 Synapse Product Development *
* Andrey Smirnov <andrew.smironv@gmail.com> *
+ * Angus Gratton <gus@projectgus.com> *
+ * Erdem U. Altunyurt <spamjunkeater@gmail.com> *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
+ * along with this program. If not, see <http://www.gnu.org/licenses/>. *
***************************************************************************/
#ifdef HAVE_CONFIG_H
#endif
#include "imp.h"
+#include <target/algorithm.h>
+#include <target/armv7m.h>
+#include <helper/types.h>
enum {
NRF51_FLASH_BASE = 0x00000000,
NRF51_UICR_BASE = 0x10001000, /* User Information
* Configuration Regsters */
- NRF51_UICR_SIZE = 252,
+ NRF51_UICR_SIZE = 0x100,
#define NRF51_UICR_REG(offset) (NRF51_UICR_BASE + offset)
struct nrf51_info {
uint32_t code_page_size;
- uint32_t code_memory_size;
struct {
bool probed;
struct nrf51_device_spec {
uint16_t hwid;
+ const char *part;
const char *variant;
const char *build_code;
unsigned int flash_size_kb;
};
+/* The known devices table below is derived from the "nRF51 Series
+ * Compatibility Matrix" document, which can be found by searching for
+ * ATTN-51 on the Nordic Semi website:
+ *
+ * http://www.nordicsemi.com/eng/content/search?SearchText=ATTN-51
+ *
+ * Up to date with Matrix v2.0, plus some additional HWIDs.
+ *
+ * The additional HWIDs apply where the build code in the matrix is
+ * shown as Gx0, Bx0, etc. In these cases the HWID in the matrix is
+ * for x==0, x!=0 means different (unspecified) HWIDs.
+ */
static const struct nrf51_device_spec nrf51_known_devices_table[] = {
+ /* nRF51822 Devices (IC rev 1). */
{
.hwid = 0x001D,
+ .part = "51822",
.variant = "QFAA",
.build_code = "CA/C0",
.flash_size_kb = 256,
},
+ {
+ .hwid = 0x0026,
+ .part = "51822",
+ .variant = "QFAB",
+ .build_code = "AA",
+ .flash_size_kb = 128,
+ },
+ {
+ .hwid = 0x0027,
+ .part = "51822",
+ .variant = "QFAB",
+ .build_code = "A0",
+ .flash_size_kb = 128,
+ },
+ {
+ .hwid = 0x0020,
+ .part = "51822",
+ .variant = "CEAA",
+ .build_code = "BA",
+ .flash_size_kb = 256,
+ },
+ {
+ .hwid = 0x002F,
+ .part = "51822",
+ .variant = "CEAA",
+ .build_code = "B0",
+ .flash_size_kb = 256,
+ },
+
+ /* nRF51822 Devices (IC rev 2). */
{
.hwid = 0x002A,
+ .part = "51822",
.variant = "QFAA",
- .build_code = "FA",
+ .build_code = "FA0",
.flash_size_kb = 256,
},
{
.hwid = 0x0044,
+ .part = "51822",
.variant = "QFAA",
- .build_code = "GC",
+ .build_code = "GC0",
.flash_size_kb = 256,
},
{
.hwid = 0x003C,
+ .part = "51822",
.variant = "QFAA",
.build_code = "G0",
.flash_size_kb = 256,
},
-
{
- .hwid = 0x0020,
- .variant = "CEAA",
- .build_code = "BA",
+ .hwid = 0x0057,
+ .part = "51822",
+ .variant = "QFAA",
+ .build_code = "G2",
.flash_size_kb = 256,
},
{
- .hwid = 0x002F,
- .variant = "CEAA",
- .build_code = "B0",
+ .hwid = 0x0058,
+ .part = "51822",
+ .variant = "QFAA",
+ .build_code = "G3",
.flash_size_kb = 256,
},
+ {
+ .hwid = 0x004C,
+ .part = "51822",
+ .variant = "QFAB",
+ .build_code = "B0",
+ .flash_size_kb = 128,
+ },
{
.hwid = 0x0040,
+ .part = "51822",
.variant = "CEAA",
- .build_code = "CA",
+ .build_code = "CA0",
.flash_size_kb = 256,
},
{
.hwid = 0x0047,
+ .part = "51822",
.variant = "CEAA",
- .build_code = "DA",
+ .build_code = "DA0",
.flash_size_kb = 256,
},
{
.hwid = 0x004D,
+ .part = "51822",
.variant = "CEAA",
- .build_code = "D0",
+ .build_code = "D00",
.flash_size_kb = 256,
},
+ /* nRF51822 Devices (IC rev 3). */
{
- .hwid = 0x0026,
+ .hwid = 0x0072,
+ .part = "51822",
+ .variant = "QFAA",
+ .build_code = "H0",
+ .flash_size_kb = 256,
+ },
+ {
+ .hwid = 0x007B,
+ .part = "51822",
.variant = "QFAB",
- .build_code = "AA",
+ .build_code = "C0",
.flash_size_kb = 128,
},
{
- .hwid = 0x0027,
- .variant = "QFAB",
+ .hwid = 0x0083,
+ .part = "51822",
+ .variant = "QFAC",
+ .build_code = "A0",
+ .flash_size_kb = 256,
+ },
+ {
+ .hwid = 0x0084,
+ .part = "51822",
+ .variant = "QFAC",
+ .build_code = "A1",
+ .flash_size_kb = 256,
+ },
+ {
+ .hwid = 0x007D,
+ .part = "51822",
+ .variant = "CDAB",
.build_code = "A0",
.flash_size_kb = 128,
},
{
- .hwid = 0x004C,
+ .hwid = 0x0079,
+ .part = "51822",
+ .variant = "CEAA",
+ .build_code = "E0",
+ .flash_size_kb = 256,
+ },
+ {
+ .hwid = 0x0087,
+ .part = "51822",
+ .variant = "CFAC",
+ .build_code = "A0",
+ .flash_size_kb = 256,
+ },
+ {
+ .hwid = 0x008F,
+ .part = "51822",
+ .variant = "QFAA",
+ .build_code = "H1",
+ .flash_size_kb = 256,
+ },
+
+ /* nRF51422 Devices (IC rev 1). */
+ {
+ .hwid = 0x001E,
+ .part = "51422",
+ .variant = "QFAA",
+ .build_code = "CA",
+ .flash_size_kb = 256,
+ },
+ {
+ .hwid = 0x0024,
+ .part = "51422",
+ .variant = "QFAA",
+ .build_code = "C0",
+ .flash_size_kb = 256,
+ },
+ {
+ .hwid = 0x0031,
+ .part = "51422",
+ .variant = "CEAA",
+ .build_code = "A0A",
+ .flash_size_kb = 256,
+ },
+
+ /* nRF51422 Devices (IC rev 2). */
+ {
+ .hwid = 0x002D,
+ .part = "51422",
+ .variant = "QFAA",
+ .build_code = "DAA",
+ .flash_size_kb = 256,
+ },
+ {
+ .hwid = 0x002E,
+ .part = "51422",
+ .variant = "QFAA",
+ .build_code = "E0",
+ .flash_size_kb = 256,
+ },
+ {
+ .hwid = 0x0061,
+ .part = "51422",
+ .variant = "QFAB",
+ .build_code = "A00",
+ .flash_size_kb = 128,
+ },
+ {
+ .hwid = 0x0050,
+ .part = "51422",
+ .variant = "CEAA",
+ .build_code = "B0",
+ .flash_size_kb = 256,
+ },
+
+ /* nRF51422 Devices (IC rev 3). */
+ {
+ .hwid = 0x0073,
+ .part = "51422",
+ .variant = "QFAA",
+ .build_code = "F0",
+ .flash_size_kb = 256,
+ },
+ {
+ .hwid = 0x007C,
+ .part = "51422",
.variant = "QFAB",
.build_code = "B0",
.flash_size_kb = 128,
},
+ {
+ .hwid = 0x0085,
+ .part = "51422",
+ .variant = "QFAC",
+ .build_code = "A0",
+ .flash_size_kb = 256,
+ },
+ {
+ .hwid = 0x0086,
+ .part = "51422",
+ .variant = "QFAC",
+ .build_code = "A1",
+ .flash_size_kb = 256,
+ },
+ {
+ .hwid = 0x007E,
+ .part = "51422",
+ .variant = "CDAB",
+ .build_code = "A0",
+ .flash_size_kb = 128,
+ },
+ {
+ .hwid = 0x007A,
+ .part = "51422",
+ .variant = "CEAA",
+ .build_code = "C0",
+ .flash_size_kb = 256,
+ },
+ {
+ .hwid = 0x0088,
+ .part = "51422",
+ .variant = "CFAC",
+ .build_code = "A0",
+ .flash_size_kb = 256,
+ },
+ /* Some early nRF51-DK (PCA10028) & nRF51-Dongle (PCA10031) boards
+ with built-in jlink seem to use engineering samples not listed
+ in the nRF51 Series Compatibility Matrix V1.0. */
+ {
+ .hwid = 0x0071,
+ .part = "51822",
+ .variant = "QFAC",
+ .build_code = "AB",
+ .flash_size_kb = 256,
+ },
};
static int nrf51_bank_is_probed(struct flash_bank *bank)
{
- struct nrf51_info *chip = (struct nrf51_info *)bank->driver_priv;
+ struct nrf51_info *chip = bank->driver_priv;
assert(chip != NULL);
return ERROR_TARGET_NOT_HALTED;
}
- *chip = (struct nrf51_info *)bank->driver_priv;
+ *chip = bank->driver_priv;
int probed = nrf51_bank_is_probed(bank);
if (probed < 0)
alive_sleep(1);
} while (timeout--);
+ LOG_DEBUG("Timed out waiting for NVMC_READY");
return ERROR_FLASH_BUSY;
}
if (bank->base == NRF51_UICR_BASE)
return ERROR_OK;
- struct nrf51_info *chip = (struct nrf51_info *)bank->driver_priv;
+ struct nrf51_info *chip = bank->driver_priv;
assert(chip != NULL);
if ((ppfc & 0xFF) == 0x00) {
LOG_ERROR("Code region 0 size was pre-programmed at the factory, can't change flash protection settings");
return ERROR_FAIL;
- };
+ }
res = target_read_u32(chip->target, NRF51_UICR_CLENR0,
&clenr0);
{
uint32_t hwid;
int res;
- struct nrf51_info *chip = (struct nrf51_info *)bank->driver_priv;
+ struct nrf51_info *chip = bank->driver_priv;
res = target_read_u32(chip->target, NRF51_FICR_CONFIGID, &hwid);
if (res != ERROR_OK) {
* bytes of the CONFIGID register */
const struct nrf51_device_spec *spec = NULL;
- for (size_t i = 0; i < ARRAY_SIZE(nrf51_known_devices_table); i++)
+ for (size_t i = 0; i < ARRAY_SIZE(nrf51_known_devices_table); i++) {
if (hwid == nrf51_known_devices_table[i].hwid) {
spec = &nrf51_known_devices_table[i];
break;
}
+ }
if (!chip->bank[0].probed && !chip->bank[1].probed) {
if (spec)
- LOG_INFO("nRF51822-%s(build code: %s) %ukB Flash",
- spec->variant, spec->build_code, spec->flash_size_kb);
+ LOG_INFO("nRF%s-%s(build code: %s) %ukB Flash",
+ spec->part, spec->variant, spec->build_code,
+ spec->flash_size_kb);
else
LOG_WARNING("Unknown device (HWID 0x%08" PRIx32 ")", hwid);
}
-
if (bank->base == NRF51_FLASH_BASE) {
+ /* The value stored in NRF51_FICR_CODEPAGESIZE is the number of bytes in one page of FLASH. */
res = target_read_u32(chip->target, NRF51_FICR_CODEPAGESIZE,
- &chip->code_page_size);
+ &chip->code_page_size);
if (res != ERROR_OK) {
LOG_ERROR("Couldn't read code page size");
return res;
}
- res = target_read_u32(chip->target, NRF51_FICR_CODESIZE,
- &chip->code_memory_size);
+ /* Note the register name is misleading,
+ * NRF51_FICR_CODESIZE is the number of pages in flash memory, not the number of bytes! */
+ uint32_t num_sectors;
+ res = target_read_u32(chip->target, NRF51_FICR_CODESIZE, &num_sectors);
if (res != ERROR_OK) {
LOG_ERROR("Couldn't read code memory size");
return res;
}
- if (spec && chip->code_memory_size != spec->flash_size_kb) {
- LOG_ERROR("Chip's reported Flash capacity does not match expected one");
- return ERROR_FAIL;
- }
+ bank->num_sectors = num_sectors;
+ bank->size = num_sectors * chip->code_page_size;
+
+ if (spec && bank->size / 1024 != spec->flash_size_kb)
+ LOG_WARNING("Chip's reported Flash capacity does not match expected one");
- bank->size = chip->code_memory_size * 1024;
- bank->num_sectors = bank->size / chip->code_page_size;
bank->sectors = calloc(bank->num_sectors,
sizeof((bank->sectors)[0]));
if (!bank->sectors)
static struct flash_sector *nrf51_find_sector_by_address(struct flash_bank *bank, uint32_t address)
{
- struct nrf51_info *chip = (struct nrf51_info *)bank->driver_priv;
+ struct nrf51_info *chip = bank->driver_priv;
for (int i = 0; i < bank->num_sectors; i++)
if (bank->sectors[i].offset <= address &&
static int nrf51_erase_all(struct nrf51_info *chip)
{
+ LOG_DEBUG("Erasing all non-volatile memory");
return nrf51_nvmc_generic_erase(chip,
NRF51_NVMC_ERASEALL,
0x00000001);
}
-static int nrf51_erase_page(struct nrf51_info *chip, struct flash_sector *sector)
+static int nrf51_erase_page(struct flash_bank *bank,
+ struct nrf51_info *chip,
+ struct flash_sector *sector)
{
int res;
- if (sector->is_protected)
+ LOG_DEBUG("Erasing page at 0x%"PRIx32, sector->offset);
+ if (sector->is_protected) {
+ LOG_ERROR("Cannot erase protected sector at 0x%" PRIx32, sector->offset);
return ERROR_FAIL;
+ }
- if (sector->offset == NRF51_UICR_BASE) {
+ if (bank->base == NRF51_UICR_BASE) {
uint32_t ppfc;
res = target_read_u32(chip->target, NRF51_FICR_PPFC,
&ppfc);
}
if ((ppfc & 0xFF) == 0xFF) {
+ /* We can't erase the UICR. Double-check to
+ see if it's already erased before complaining. */
+ default_flash_blank_check(bank);
+ if (sector->is_erased == 1)
+ return ERROR_OK;
+
LOG_ERROR("The chip was not pre-programmed with SoftDevice stack and UICR cannot be erased separately. Please issue mass erase before trying to write to this region");
return ERROR_FAIL;
- };
+ }
res = nrf51_nvmc_generic_erase(chip,
NRF51_NVMC_ERASEUICR,
return res;
}
-static int nrf51_write_page(struct flash_bank *bank, uint32_t offset, const uint8_t *buffer)
+static const uint8_t nrf51_flash_write_code[] = {
+ /* See contrib/loaders/flash/cortex-m0.S */
+/* <wait_fifo>: */
+ 0x0d, 0x68, /* ldr r5, [r1, #0] */
+ 0x00, 0x2d, /* cmp r5, #0 */
+ 0x0b, 0xd0, /* beq.n 1e <exit> */
+ 0x4c, 0x68, /* ldr r4, [r1, #4] */
+ 0xac, 0x42, /* cmp r4, r5 */
+ 0xf9, 0xd0, /* beq.n 0 <wait_fifo> */
+ 0x20, 0xcc, /* ldmia r4!, {r5} */
+ 0x20, 0xc3, /* stmia r3!, {r5} */
+ 0x94, 0x42, /* cmp r4, r2 */
+ 0x01, 0xd3, /* bcc.n 18 <no_wrap> */
+ 0x0c, 0x46, /* mov r4, r1 */
+ 0x08, 0x34, /* adds r4, #8 */
+/* <no_wrap>: */
+ 0x4c, 0x60, /* str r4, [r1, #4] */
+ 0x04, 0x38, /* subs r0, #4 */
+ 0xf0, 0xd1, /* bne.n 0 <wait_fifo> */
+/* <exit>: */
+ 0x00, 0xbe /* bkpt 0x0000 */
+};
+
+
+/* Start a low level flash write for the specified region */
+static int nrf51_ll_flash_write(struct nrf51_info *chip, uint32_t offset, const uint8_t *buffer, uint32_t bytes)
{
- assert(offset % 4 == 0);
+ struct target *target = chip->target;
+ uint32_t buffer_size = 8192;
+ struct working_area *write_algorithm;
+ struct working_area *source;
+ uint32_t address = NRF51_FLASH_BASE + offset;
+ struct reg_param reg_params[4];
+ struct armv7m_algorithm armv7m_info;
+ int retval = ERROR_OK;
+
+
+ LOG_DEBUG("Writing buffer to flash offset=0x%"PRIx32" bytes=0x%"PRIx32, offset, bytes);
+ assert(bytes % 4 == 0);
+
+ /* allocate working area with flash programming code */
+ if (target_alloc_working_area(target, sizeof(nrf51_flash_write_code),
+ &write_algorithm) != ERROR_OK) {
+ LOG_WARNING("no working area available, falling back to slow memory writes");
+
+ for (; bytes > 0; bytes -= 4) {
+ retval = target_write_memory(chip->target, offset, 4, 1, buffer);
+ if (retval != ERROR_OK)
+ return retval;
+
+ retval = nrf51_wait_for_nvmc(chip);
+ if (retval != ERROR_OK)
+ return retval;
+
+ offset += 4;
+ buffer += 4;
+ }
- int res = ERROR_FAIL;
- struct nrf51_info *chip = (struct nrf51_info *)bank->driver_priv;
- struct flash_sector *sector = nrf51_find_sector_by_address(bank, offset);
+ return ERROR_OK;
+ }
- if (!sector)
- goto error;
+ LOG_WARNING("using fast async flash loader. This is currently supported");
+ LOG_WARNING("only with ST-Link and CMSIS-DAP. If you have issues, add");
+ LOG_WARNING("\"set WORKAREASIZE 0\" before sourcing nrf51.cfg to disable it");
+
+ retval = target_write_buffer(target, write_algorithm->address,
+ sizeof(nrf51_flash_write_code),
+ nrf51_flash_write_code);
+ if (retval != ERROR_OK)
+ return retval;
+
+ /* memory buffer */
+ while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK) {
+ buffer_size /= 2;
+ buffer_size &= ~3UL; /* Make sure it's 4 byte aligned */
+ if (buffer_size <= 256) {
+ /* free working area, write algorithm already allocated */
+ target_free_working_area(target, write_algorithm);
+
+ LOG_WARNING("No large enough working area available, can't do block memory writes");
+ return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+ }
+ }
- if (sector->is_protected)
- goto error;
+ armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
+ armv7m_info.core_mode = ARM_MODE_THREAD;
- if (!sector->is_erased) {
- res = nrf51_erase_page(chip, sector);
- if (res != ERROR_OK) {
- LOG_ERROR("Failed to erase sector @ 0x%08"PRIx32, sector->offset);
+ init_reg_param(®_params[0], "r0", 32, PARAM_IN_OUT); /* byte count */
+ init_reg_param(®_params[1], "r1", 32, PARAM_OUT); /* buffer start */
+ init_reg_param(®_params[2], "r2", 32, PARAM_OUT); /* buffer end */
+ init_reg_param(®_params[3], "r3", 32, PARAM_IN_OUT); /* target address */
+
+ buf_set_u32(reg_params[0].value, 0, 32, bytes);
+ buf_set_u32(reg_params[1].value, 0, 32, source->address);
+ buf_set_u32(reg_params[2].value, 0, 32, source->address + source->size);
+ buf_set_u32(reg_params[3].value, 0, 32, address);
+
+ retval = target_run_flash_async_algorithm(target, buffer, bytes/4, 4,
+ 0, NULL,
+ 4, reg_params,
+ source->address, source->size,
+ write_algorithm->address, 0,
+ &armv7m_info);
+
+ target_free_working_area(target, source);
+ target_free_working_area(target, write_algorithm);
+
+ destroy_reg_param(®_params[0]);
+ destroy_reg_param(®_params[1]);
+ destroy_reg_param(®_params[2]);
+ destroy_reg_param(®_params[3]);
+
+ return retval;
+}
+
+/* Check and erase flash sectors in specified range then start a low level page write.
+ start/end must be sector aligned.
+*/
+static int nrf51_write_pages(struct flash_bank *bank, uint32_t start, uint32_t end, const uint8_t *buffer)
+{
+ int res = ERROR_FAIL;
+ struct nrf51_info *chip = bank->driver_priv;
+ struct flash_sector *sector;
+ uint32_t offset;
+
+ assert(start % chip->code_page_size == 0);
+ assert(end % chip->code_page_size == 0);
+
+ /* Erase all sectors */
+ for (offset = start; offset < end; offset += chip->code_page_size) {
+ sector = nrf51_find_sector_by_address(bank, offset);
+ if (!sector) {
+ LOG_ERROR("Invalid sector @ 0x%08"PRIx32, offset);
+ return ERROR_FLASH_SECTOR_INVALID;
+ }
+
+ if (sector->is_protected) {
+ LOG_ERROR("Can't erase protected sector @ 0x%08"PRIx32, offset);
goto error;
}
+
+ if (sector->is_erased != 1) { /* 1 = erased, 0= not erased, -1 = unknown */
+ res = nrf51_erase_page(bank, chip, sector);
+ if (res != ERROR_OK) {
+ LOG_ERROR("Failed to erase sector @ 0x%08"PRIx32, sector->offset);
+ goto error;
+ }
+ }
+ sector->is_erased = 0;
}
res = nrf51_nvmc_write_enable(chip);
if (res != ERROR_OK)
goto error;
- sector->is_erased = 0;
- res = target_write_memory(bank->target, offset, 4,
- chip->code_page_size / 4, buffer);
+ res = nrf51_ll_flash_write(chip, start, buffer, (end - start));
if (res != ERROR_OK)
goto set_read_only;
set_read_only:
nrf51_nvmc_read_only(chip);
error:
- LOG_ERROR("Failed to write sector @ 0x%08"PRIx32, sector->offset);
+ LOG_ERROR("Failed to write to nrf51 flash");
return res;
}
/* For each sector to be erased */
for (int s = first; s <= last && res == ERROR_OK; s++)
- res = nrf51_erase_page(chip, &bank->sectors[s]);
+ res = nrf51_erase_page(bank, chip, &bank->sectors[s]);
return res;
}
struct nrf51_info *chip,
const uint8_t *buffer, uint32_t offset, uint32_t count)
{
- int res;
- struct {
- uint32_t start, end;
- } region;
- region.start = offset;
- region.end = offset + count;
+ int res;
+ /* Need to perform reads to fill any gaps we need to preserve in the first page,
+ before the start of buffer, or in the last page, after the end of buffer */
+ uint32_t first_page = offset/chip->code_page_size;
+ uint32_t last_page = DIV_ROUND_UP(offset+count, chip->code_page_size);
- struct {
- size_t length;
- const uint8_t *buffer;
- } start_extra, end_extra;
+ uint32_t first_page_offset = first_page * chip->code_page_size;
+ uint32_t last_page_offset = last_page * chip->code_page_size;
- start_extra.length = region.start % chip->code_page_size;
- start_extra.buffer = buffer;
- end_extra.length = region.end % chip->code_page_size;
- end_extra.buffer = buffer + count - end_extra.length;
+ LOG_DEBUG("Padding write from 0x%08"PRIx32"-0x%08"PRIx32" as 0x%08"PRIx32"-0x%08"PRIx32,
+ offset, offset+count, first_page_offset, last_page_offset);
- if (start_extra.length) {
- uint8_t page[chip->code_page_size];
+ uint32_t page_cnt = last_page - first_page;
+ uint8_t buffer_to_flash[page_cnt*chip->code_page_size];
+ /* Fill in any space between start of first page and start of buffer */
+ uint32_t pre = offset - first_page_offset;
+ if (pre > 0) {
res = target_read_memory(bank->target,
- region.start - start_extra.length,
- 1, start_extra.length, page);
- if (res != ERROR_OK)
- return res;
-
- memcpy(page + start_extra.length,
- start_extra.buffer,
- chip->code_page_size - start_extra.length);
-
- res = nrf51_write_page(bank,
- region.start - start_extra.length,
- page);
+ first_page_offset,
+ 1,
+ pre,
+ buffer_to_flash);
if (res != ERROR_OK)
return res;
}
- if (end_extra.length) {
- uint8_t page[chip->code_page_size];
+ /* Fill in main contents of buffer */
+ memcpy(buffer_to_flash+pre, buffer, count);
+ /* Fill in any space between end of buffer and end of last page */
+ uint32_t post = last_page_offset - (offset+count);
+ if (post > 0) {
/* Retrieve the full row contents from Flash */
res = target_read_memory(bank->target,
- region.end,
- 1,
- (chip->code_page_size - end_extra.length),
- page + end_extra.length);
- if (res != ERROR_OK)
- return res;
-
- memcpy(page, end_extra.buffer, end_extra.length);
-
- res = nrf51_write_page(bank,
- region.end - end_extra.length,
- page);
+ offset + count,
+ 1,
+ post,
+ buffer_to_flash+pre+count);
if (res != ERROR_OK)
return res;
}
-
- region.start += start_extra.length;
- region.end -= end_extra.length;
-
- for (uint32_t address = region.start; address < region.end;
- address += chip->code_page_size) {
- res = nrf51_write_page(bank, address, &buffer[address - region.start]);
-
- if (res != ERROR_OK)
- return res;
-
- }
-
- return ERROR_OK;
+ return nrf51_write_pages(bank, first_page_offset, last_page_offset, buffer_to_flash);
}
static int nrf51_uicr_flash_write(struct flash_bank *bank,
if (res != ERROR_OK)
return res;
- if (!sector->is_erased) {
- res = nrf51_erase_page(chip, sector);
+ if (sector->is_erased != 1) {
+ res = nrf51_erase_page(bank, chip, sector);
if (res != ERROR_OK)
return res;
}
memcpy(&uicr[offset], buffer, count);
- res = target_write_memory(bank->target,
- NRF51_UICR_BASE,
- 4,
- NRF51_UICR_SIZE / 4,
- uicr);
+ res = nrf51_ll_flash_write(chip, NRF51_UICR_BASE, uicr, NRF51_UICR_SIZE);
if (res != ERROR_OK) {
nrf51_nvmc_read_only(chip);
return res;
LOG_ERROR("Code region 0 size was pre-programmed at the factory, "
"mass erase command won't work.");
return ERROR_FAIL;
- };
+ }
res = nrf51_erase_all(chip);
if (res != ERROR_OK) {
if (res != ERROR_OK)
return res;
- struct {
- uint32_t address, value;
+ static struct {
+ const uint32_t address;
+ uint32_t value;
} ficr[] = {
{ .address = NRF51_FICR_CODEPAGESIZE },
{ .address = NRF51_FICR_CODESIZE },
"reset value for XTALFREQ: %"PRIx32"\n"
"firmware id: 0x%04"PRIx32,
ficr[0].value,
- ficr[1].value,
+ (ficr[1].value * ficr[0].value) / 1024,
(ficr[2].value == 0xFFFFFFFF) ? 0 : ficr[2].value / 1024,
((ficr[3].value & 0xFF) == 0x00) ? "present" : "not present",
ficr[4].value,
projects / fw / openocd / blobdiff