* by Nemui Trinomius *
* nemuisan_kawausogasuki@live.jp *
* *
+ * LPC8N04/HNS31xx support Copyright (C) 2018 *
+ * by Jean-Christian de Rivaz jcdr [at] innodelec [dot] ch *
+ * *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
+ * along with this program. If not, see <http://www.gnu.org/licenses/>. *
***************************************************************************/
#ifdef HAVE_CONFIG_H
/**
* @file
- * flash programming support for NXP LPC8xx,LPC1xxx,LPC4xxx,LP5410x and LPC2xxx devices.
+ * flash programming support for NXP LPC8xx,LPC1xxx,LPC4xxx,LP5410x,LPC2xxx and NHS31xx devices.
*
* @todo Provide a way to update CCLK after declaring the flash bank. The value which is correct after chip reset will
* rarely still work right after the clocks switch to use the PLL (e.g. 4MHz --> 100 MHz).
* lpc800:
* - 810 | 1 | 2 (tested with LPC810/LPC811/LPC812)
* - 822 | 4 (tested with LPC824)
+ * - 8N04
+ * - NHS31xx (tested with NHS3100)
+ * - 844 | 5 (tested with LPC845)
*
* lpc1100:
* - 11xx
* - 408x
* - 81x
* - 82x
+ * - 8N04
+ * - NHS31xx
*/
/* Part IDs for autodetection */
#define LPC1317 0x1A020525
#define LPC1342 0x3D01402B
#define LPC1343 0x3D00002B
+#define LPC1343_1 0x3000002B
#define LPC1345 0x28010541
#define LPC1346 0x08018542
#define LPC1347 0x08020543
#define LPC824_201 0x00008241
#define LPC824_201_1 0x00008242
+#define LPC8N04 0x00008A04
+#define NHS3100 0x4e310020
+#define NHS3152 0x4e315220
+#define NHS3153 0x4e315320 /* Only specified in Rev.1 of the datasheet */
+
+#define LPC844_201 0x00008441
+#define LPC844_201_1 0x00008442
+#define LPC844_201_2 0x00008444
+
+#define LPC845_301 0x00008451
+#define LPC845_301_1 0x00008452
+#define LPC845_301_2 0x00008453
+#define LPC845_301_3 0x00008454
+
#define IAP_CODE_LEN 0x34
+#define LPC11xx_REG_SECTORS 24
+
typedef enum {
lpc2000_v1,
lpc2000_v2,
int checksum_vector;
uint32_t iap_max_stack;
uint32_t lpc4300_bank;
+ uint32_t iap_entry_alternative;
bool probed;
};
case 16 * 1024:
bank->num_sectors = 16;
break;
+ case 30 * 1024:
+ lpc2000_info->cmd51_max_buffer = 1024; /* For LPC8N04 and NHS31xx, have 8kB of SRAM */
+ bank->num_sectors = 30; /* There have only 30kB of writable Flash out of 32kB */
+ break;
case 32 * 1024:
lpc2000_info->cmd51_max_buffer = 1024; /* For LPC824, has 8kB of SRAM */
bank->num_sectors = 32;
break;
+ case 64 * 1024:
+ lpc2000_info->cmd51_max_buffer = 1024; /* For LPC844, has 8kB of SRAM */
+ bank->num_sectors = 64;
+ break;
default:
LOG_ERROR("BUG: unknown bank->size encountered");
exit(-1);
exit(-1);
}
lpc2000_info->cmd51_max_buffer = 512; /* smallest MCU in the series, LPC1110, has 1 kB of SRAM */
- bank->num_sectors = bank->size / 4096;
+ unsigned int large_sectors = 0;
+ unsigned int normal_sectors = bank->size / 4096;
+
+ if (normal_sectors > LPC11xx_REG_SECTORS) {
+ large_sectors = (normal_sectors - LPC11xx_REG_SECTORS) / 8;
+ normal_sectors = LPC11xx_REG_SECTORS;
+ }
+
+ bank->num_sectors = normal_sectors + large_sectors;
bank->sectors = malloc(sizeof(struct flash_sector) * bank->num_sectors);
for (int i = 0; i < bank->num_sectors; i++) {
bank->sectors[i].offset = offset;
- /* all sectors are 4kB-sized */
- bank->sectors[i].size = 4 * 1024;
+ bank->sectors[i].size = (i < LPC11xx_REG_SECTORS ? 4 : 32) * 1024;
offset += bank->sectors[i].size;
bank->sectors[i].is_erased = -1;
bank->sectors[i].is_protected = 1;
}
int retval = target_write_memory(target, (*iap_working_area)->address, 4, 2, jump_gate);
- if (retval != ERROR_OK)
- LOG_ERROR("Write memory at address 0x%8.8" PRIx32 " failed (check work_area definition)",
+ if (retval != ERROR_OK) {
+ LOG_ERROR("Write memory at address " TARGET_ADDR_FMT " failed (check work_area definition)",
(*iap_working_area)->address);
+ target_free_working_area(target, *iap_working_area);
+ }
return retval;
}
exit(-1);
}
+ if (lpc2000_info->iap_entry_alternative != 0x0)
+ iap_entry_point = lpc2000_info->iap_entry_alternative;
+
struct mem_param mem_params[2];
/* command parameter table */
if (strcmp(CMD_ARGV[8], "calc_checksum") == 0)
lpc2000_info->calc_checksum = 1;
}
+ if (CMD_ARGC >= 10 && !lpc2000_info->iap_entry_alternative)
+ COMMAND_PARSE_NUMBER(u32, CMD_ARGV[9], lpc2000_info->iap_entry_alternative);
return ERROR_OK;
}
return retval;
}
-static int lpc2000_protect(struct flash_bank *bank, int set, int first, int last)
-{
- /* can't protect/unprotect on the lpc2000 */
- return ERROR_OK;
-}
-
static int lpc2000_write(struct flash_bank *bank, const uint8_t *buffer, uint32_t offset, uint32_t count)
{
struct target *target = bank->target;
free(last_buffer);
}
- LOG_DEBUG("writing 0x%" PRIx32 " bytes to address 0x%" PRIx32, thisrun_bytes,
- bank->base + offset + bytes_written);
+ LOG_DEBUG("writing 0x%" PRIx32 " bytes to address " TARGET_ADDR_FMT,
+ thisrun_bytes, bank->base + offset + bytes_written);
/* Write data */
param_table[0] = bank->base + offset + bytes_written;
case LPC1313_1:
case LPC1315:
case LPC1343:
+ case LPC1343_1:
case LPC1345:
lpc2000_info->variant = lpc1100;
bank->size = 32 * 1024;
bank->size = 32 * 1024;
break;
+ case LPC8N04:
+ case NHS3100:
+ case NHS3152:
+ case NHS3153:
+ lpc2000_info->variant = lpc800;
+ bank->size = 30 * 1024;
+ break;
+
+ case LPC844_201:
+ case LPC844_201_1:
+ case LPC844_201_2:
+ case LPC845_301:
+ case LPC845_301_1:
+ case LPC845_301_2:
+ case LPC845_301_3:
+ lpc2000_info->variant = lpc800;
+ bank->size = 64 * 1024;
+ break;
+
default:
- LOG_ERROR("BUG: unknown Part ID encountered: 0x%x", part_id);
+ LOG_ERROR("BUG: unknown Part ID encountered: 0x%" PRIx32, part_id);
exit(-1);
}
status = get_lpc2000_part_id(bank, &part_id);
if (status == LPC2000_CMD_SUCCESS)
LOG_INFO("If auto-detection fails for this part, please email "
- "openocd-devel@lists.sourceforge.net, citing part id 0x%x.\n", part_id);
+ "openocd-devel@lists.sourceforge.net, citing part id 0x%" PRIx32 ".\n", part_id);
}
lpc2000_build_sector_list(bank);
return lpc2000_iap_blank_check(bank, 0, bank->num_sectors - 1);
}
-static int lpc2000_protect_check(struct flash_bank *bank)
-{
- /* sectors are always protected */
- return ERROR_OK;
-}
-
static int get_lpc2000_info(struct flash_bank *bank, char *buf, int buf_size)
{
struct lpc2000_flash_bank *lpc2000_info = bank->driver_priv;
int status_code = get_lpc2000_part_id(bank, &part_id);
if (status_code != 0x0) {
if (status_code == ERROR_FLASH_OPERATION_FAILED) {
- command_print(CMD_CTX, "no sufficient working area specified, can't access LPC2000 IAP interface");
+ command_print(CMD, "no sufficient working area specified, can't access LPC2000 IAP interface");
} else
- command_print(CMD_CTX, "lpc2000 IAP returned status code %i", status_code);
+ command_print(CMD, "lpc2000 IAP returned status code %i", status_code);
} else
- command_print(CMD_CTX, "lpc2000 part id: 0x%8.8" PRIx32, part_id);
+ command_print(CMD, "lpc2000 part id: 0x%8.8" PRIx32, part_id);
return retval;
}
COMMAND_REGISTRATION_DONE
};
-struct flash_driver lpc2000_flash = {
+const struct flash_driver lpc2000_flash = {
.name = "lpc2000",
.commands = lpc2000_command_handlers,
.flash_bank_command = lpc2000_flash_bank_command,
.erase = lpc2000_erase,
- .protect = lpc2000_protect,
.write = lpc2000_write,
.read = default_flash_read,
.probe = lpc2000_probe,
.auto_probe = lpc2000_probe,
.erase_check = lpc2000_erase_check,
- .protect_check = lpc2000_protect_check,
.info = get_lpc2000_info,
+ .free_driver_priv = default_flash_free_driver_priv,
};
projects / fw / openocd / blobdiff