#include "config.h"
#endif
+#include "jtag/interface.h"
#include "imp.h"
#include <helper/binarybuffer.h>
#include <target/algorithm.h>
#include <target/armv7m.h>
+#include <target/cortex_m.h>
/*
* Implementation Notes
* variants also have FlexNVM and FlexRAM, which always appear
* together.
*
- * A given Kinetis chip may have 2 or 4 blocks of flash. Here we map
+ * A given Kinetis chip may have 1, 2 or 4 blocks of flash. Here we map
* each block to a separate bank. Each block size varies by chip and
* may be determined by the read-only SIM_FCFG1 register. The sector
- * size within each bank/block varies by the chip granularity as
- * described below.
+ * size within each bank/block varies by chip, and may be 1, 2 or 4k.
+ * The sector size may be different for flash and FlexNVM.
*
- * Kinetis offers four different of flash granularities applicable
- * across the chip families. The granularity is apparently reflected
- * by at least the reference manual suffix. For example, for chip
- * MK60FN1M0VLQ12, reference manual K60P144M150SF3RM ends in "SF3RM",
- * where the "3" indicates there are four flash blocks with 4kiB
- * sectors. All possible granularities are indicated below.
- *
- * The first half of the flash (1 or 2 blocks, depending on the
- * granularity) is always Program Flash and always starts at address
- * 0x00000000. The "PFLSH" flag, bit 23 of the read-only SIM_FCFG2
- * register, determines whether the second half of the flash is also
- * Program Flash or FlexNVM+FlexRAM. When PFLSH is set, the second
- * half of flash is Program Flash and is contiguous in the memory map
- * from the first half. When PFLSH is clear, the second half of flash
- * is FlexNVM and always starts at address 0x10000000. FlexRAM, which
- * is also present when PFLSH is clear, always starts at address
- * 0x14000000.
+ * The first half of the flash (1 or 2 blocks) is always Program Flash
+ * and always starts at address 0x00000000. The "PFLSH" flag, bit 23
+ * of the read-only SIM_FCFG2 register, determines whether the second
+ * half of the flash is also Program Flash or FlexNVM+FlexRAM. When
+ * PFLSH is set, the second from the first half. When PFLSH is clear,
+ * the second half of flash is FlexNVM and always starts at address
+ * 0x10000000. FlexRAM, which is also present when PFLSH is clear,
+ * always starts at address 0x14000000.
*
* The Flash Memory Module provides a register set where flash
* commands are loaded to perform flash operations like erase and
* program. Different commands are available depending on whether
* Program Flash or FlexNVM/FlexRAM is being manipulated. Although
* the commands used are quite consistent between flash blocks, the
- * parameters they accept differ according to the flash granularity.
- * Some Kinetis chips have different granularity between Program Flash
- * and FlexNVM/FlexRAM, so flash command arguments may differ between
- * blocks in the same chip.
+ * parameters they accept differ according to the flash sector size.
*
*/
-static const struct {
- unsigned pflash_sector_size_bytes;
- unsigned nvm_sector_size_bytes;
- unsigned num_blocks;
-} kinetis_flash_params[4] = {
- { 1<<10, 1<<10, 2 },
- { 2<<10, 1<<10, 2 },
- { 2<<10, 2<<10, 2 },
- { 4<<10, 4<<10, 4 }
-};
-
/* Addressess */
#define FLEXRAM 0x14000000
#define FTFx_FSTAT 0x40020000
#define FTFx_FCCOB3 0x40020004
#define FTFx_FPROT3 0x40020010
#define SIM_SDID 0x40048024
+#define SIM_SOPT1 0x40047000
#define SIM_FCFG1 0x4004804c
#define SIM_FCFG2 0x40048050
#define FTFx_CMD_SETFLEXRAM 0x81
#define FTFx_CMD_MASSERASE 0x44
-/* The Kinetis K series uses the following SDID layout :
+/* The older Kinetis K series uses the following SDID layout :
* Bit 31-16 : 0
* Bit 15-12 : REVID
* Bit 11-7 : DIEID
* Bit 6-4 : FAMID
* Bit 3-0 : PINID
*
- * The Kinetis KL series uses the following SDID layout :
+ * The newer Kinetis series uses the following SDID layout :
* Bit 31-28 : FAMID
* Bit 27-24 : SUBFAMID
* Bit 23-20 : SERIESID
* Bit 6-4 : Reserved (0)
* Bit 3-0 : PINID
*
- * SERIESID should be 1 for the KL-series so we assume that if
- * bits 31-16 are 0 then it's a K-series MCU.
+ * We assume that if bits 31-16 are 0 then it's an older
+ * K-series MCU.
*/
+#define KINETIS_SOPT1_RAMSIZE_MASK 0x0000F000
+#define KINETIS_SOPT1_RAMSIZE_K24FN1M 0x0000B000
+
#define KINETIS_SDID_K_SERIES_MASK 0x0000FFFF
#define KINETIS_SDID_DIEID_MASK 0x00000F80
#define KINETIS_SDID_DIEID_K_A 0x00000100
#define KINETIS_SDID_DIEID_K_B 0x00000200
#define KINETIS_SDID_DIEID_KL 0x00000000
+#define KINETIS_SDID_DIEID_K24FN1M 0x00000300 /* Detect Errata 7534 */
/* We can't rely solely on the FAMID field to determine the MCU
* type since some FAMID values identify multiple MCUs with
#define KINETIS_K_SDID_K60_M150 0x000001C0
#define KINETIS_K_SDID_K70_M150 0x000001D0
-#define KINETIS_KL_SDID_SERIESID_MASK 0x00F00000
-#define KINETIS_KL_SDID_SERIESID_KL 0x00100000
+#define KINETIS_SDID_SERIESID_MASK 0x00F00000
+#define KINETIS_SDID_SERIESID_K 0x00000000
+#define KINETIS_SDID_SERIESID_KL 0x00100000
+#define KINETIS_SDID_SERIESID_KW 0x00500000
+#define KINETIS_SDID_SERIESID_KV 0x00600000
+
+#define KINETIS_SDID_SUBFAMID_MASK 0x0F000000
+#define KINETIS_SDID_SUBFAMID_KX0 0x00000000
+#define KINETIS_SDID_SUBFAMID_KX1 0x01000000
+#define KINETIS_SDID_SUBFAMID_KX2 0x02000000
+#define KINETIS_SDID_SUBFAMID_KX3 0x03000000
+#define KINETIS_SDID_SUBFAMID_KX4 0x04000000
+#define KINETIS_SDID_SUBFAMID_KX5 0x05000000
+#define KINETIS_SDID_SUBFAMID_KX6 0x06000000
+
+#define KINETIS_SDID_FAMILYID_MASK 0xF0000000
+#define KINETIS_SDID_FAMILYID_K0X 0x00000000
+#define KINETIS_SDID_FAMILYID_K1X 0x10000000
+#define KINETIS_SDID_FAMILYID_K2X 0x20000000
+#define KINETIS_SDID_FAMILYID_K3X 0x30000000
+#define KINETIS_SDID_FAMILYID_K4X 0x40000000
+#define KINETIS_SDID_FAMILYID_K6X 0x60000000
+#define KINETIS_SDID_FAMILYID_K7X 0x70000000
struct kinetis_flash_bank {
- unsigned granularity;
unsigned bank_ordinal;
uint32_t sector_size;
+ uint32_t max_flash_prog_size;
uint32_t protection_size;
- uint32_t klxx;
uint32_t sim_sdid;
uint32_t sim_fcfg1;
FC_FLEX_NVM,
FC_FLEX_RAM,
} flash_class;
+
+ enum {
+ FS_PROGRAM_SECTOR = 1,
+ FS_PROGRAM_LONGWORD = 2,
+ FS_PROGRAM_PHRASE = 4, /* Unsupported */
+ } flash_support;
+};
+
+#define MDM_REG_STAT 0x00
+#define MDM_REG_CTRL 0x04
+#define MDM_REG_ID 0xfc
+
+#define MDM_STAT_FMEACK (1<<0)
+#define MDM_STAT_FREADY (1<<1)
+#define MDM_STAT_SYSSEC (1<<2)
+#define MDM_STAT_SYSRES (1<<3)
+#define MDM_STAT_FMEEN (1<<5)
+#define MDM_STAT_BACKDOOREN (1<<6)
+#define MDM_STAT_LPEN (1<<7)
+#define MDM_STAT_VLPEN (1<<8)
+#define MDM_STAT_LLSMODEXIT (1<<9)
+#define MDM_STAT_VLLSXMODEXIT (1<<10)
+#define MDM_STAT_CORE_HALTED (1<<16)
+#define MDM_STAT_CORE_SLEEPDEEP (1<<17)
+#define MDM_STAT_CORESLEEPING (1<<18)
+
+#define MEM_CTRL_FMEIP (1<<0)
+#define MEM_CTRL_DBG_DIS (1<<1)
+#define MEM_CTRL_DBG_REQ (1<<2)
+#define MEM_CTRL_SYS_RES_REQ (1<<3)
+#define MEM_CTRL_CORE_HOLD_RES (1<<4)
+#define MEM_CTRL_VLLSX_DBG_REQ (1<<5)
+#define MEM_CTRL_VLLSX_DBG_ACK (1<<6)
+#define MEM_CTRL_VLLSX_STAT_ACK (1<<7)
+
+#define MDM_ACCESS_TIMEOUT 3000 /* iterations */
+
+static int kinetis_mdm_write_register(struct adiv5_dap *dap, unsigned reg, uint32_t value)
+{
+ int retval;
+ LOG_DEBUG("MDM_REG[0x%02x] <- %08" PRIX32, reg, value);
+
+ retval = dap_queue_ap_write(dap, reg, value);
+ if (retval != ERROR_OK) {
+ LOG_DEBUG("MDM: failed to queue a write request");
+ return retval;
+ }
+
+ retval = dap_run(dap);
+ if (retval != ERROR_OK) {
+ LOG_DEBUG("MDM: dap_run failed");
+ return retval;
+ }
+
+
+ return ERROR_OK;
+}
+
+static int kinetis_mdm_read_register(struct adiv5_dap *dap, unsigned reg, uint32_t *result)
+{
+ int retval;
+ retval = dap_queue_ap_read(dap, reg, result);
+ if (retval != ERROR_OK) {
+ LOG_DEBUG("MDM: failed to queue a read request");
+ return retval;
+ }
+
+ retval = dap_run(dap);
+ if (retval != ERROR_OK) {
+ LOG_DEBUG("MDM: dap_run failed");
+ return retval;
+ }
+
+ LOG_DEBUG("MDM_REG[0x%02x]: %08" PRIX32, reg, *result);
+ return ERROR_OK;
+}
+
+static int kinetis_mdm_poll_register(struct adiv5_dap *dap, unsigned reg, uint32_t mask, uint32_t value)
+{
+ uint32_t val;
+ int retval;
+ int timeout = MDM_ACCESS_TIMEOUT;
+
+ do {
+ retval = kinetis_mdm_read_register(dap, reg, &val);
+ if (retval != ERROR_OK || (val & mask) == value)
+ return retval;
+
+ alive_sleep(1);
+ } while (timeout--);
+
+ LOG_DEBUG("MDM: polling timed out");
+ return ERROR_FAIL;
+}
+
+/*
+ * This function implements the procedure to mass erase the flash via
+ * SWD/JTAG on Kinetis K and L series of devices as it is described in
+ * AN4835 "Production Flash Programming Best Practices for Kinetis K-
+ * and L-series MCUs" Section 4.2.1
+ */
+COMMAND_HANDLER(kinetis_mdm_mass_erase)
+{
+ struct target *target = get_current_target(CMD_CTX);
+ struct cortex_m_common *cortex_m = target_to_cm(target);
+ struct adiv5_dap *dap = cortex_m->armv7m.arm.dap;
+
+ if (!dap) {
+ LOG_ERROR("Cannot perform mass erase with a high-level adapter");
+ return ERROR_FAIL;
+ }
+
+ int retval;
+ const uint8_t original_ap = dap->ap_current;
+
+ /*
+ * ... Power on the processor, or if power has already been
+ * applied, assert the RESET pin to reset the processor. For
+ * devices that do not have a RESET pin, write the System
+ * Reset Request bit in the MDM-AP control register after
+ * establishing communication...
+ */
+
+ /* assert SRST */
+ if (jtag_get_reset_config() & RESET_HAS_SRST)
+ adapter_assert_reset();
+ else
+ LOG_WARNING("Attempting mass erase without hardware reset. This is not reliable; "
+ "it's recommended you connect SRST and use ``reset_config srst_only''.");
+
+ dap_ap_select(dap, 1);
+
+ retval = kinetis_mdm_write_register(dap, MDM_REG_CTRL, MEM_CTRL_SYS_RES_REQ);
+ if (retval != ERROR_OK)
+ return retval;
+
+ /*
+ * ... Read the MDM-AP status register until the Flash Ready bit sets...
+ */
+ retval = kinetis_mdm_poll_register(dap, MDM_REG_STAT,
+ MDM_STAT_FREADY | MDM_STAT_SYSRES,
+ MDM_STAT_FREADY);
+ if (retval != ERROR_OK) {
+ LOG_ERROR("MDM : flash ready timeout");
+ return retval;
+ }
+
+ /*
+ * ... Write the MDM-AP control register to set the Flash Mass
+ * Erase in Progress bit. This will start the mass erase
+ * process...
+ */
+ retval = kinetis_mdm_write_register(dap, MDM_REG_CTRL,
+ MEM_CTRL_SYS_RES_REQ | MEM_CTRL_FMEIP);
+ if (retval != ERROR_OK)
+ return retval;
+
+ /* As a sanity check make sure that device started mass erase procedure */
+ retval = kinetis_mdm_poll_register(dap, MDM_REG_STAT,
+ MDM_STAT_FMEACK, MDM_STAT_FMEACK);
+ if (retval != ERROR_OK)
+ return retval;
+
+ /*
+ * ... Read the MDM-AP control register until the Flash Mass
+ * Erase in Progress bit clears...
+ */
+ retval = kinetis_mdm_poll_register(dap, MDM_REG_CTRL,
+ MEM_CTRL_FMEIP,
+ 0);
+ if (retval != ERROR_OK)
+ return retval;
+
+ /*
+ * ... Negate the RESET signal or clear the System Reset Request
+ * bit in the MDM-AP control register...
+ */
+ retval = kinetis_mdm_write_register(dap, MDM_REG_CTRL, 0);
+ if (retval != ERROR_OK)
+ return retval;
+
+ if (jtag_get_reset_config() & RESET_HAS_SRST)
+ adapter_deassert_reset();
+
+ dap_ap_select(dap, original_ap);
+ return ERROR_OK;
+}
+
+static const uint32_t kinetis_known_mdm_ids[] = {
+ 0x001C0000, /* Kinetis-K Series */
+ 0x001C0020, /* Kinetis-L/M/V/E Series */
};
+/*
+ * This function implements the procedure to connect to
+ * SWD/JTAG on Kinetis K and L series of devices as it is described in
+ * AN4835 "Production Flash Programming Best Practices for Kinetis K-
+ * and L-series MCUs" Section 4.1.1
+ */
+COMMAND_HANDLER(kinetis_check_flash_security_status)
+{
+ struct target *target = get_current_target(CMD_CTX);
+ struct cortex_m_common *cortex_m = target_to_cm(target);
+ struct adiv5_dap *dap = cortex_m->armv7m.arm.dap;
+
+ if (!dap) {
+ LOG_WARNING("Cannot check flash security status with a high-level adapter");
+ return ERROR_OK;
+ }
+
+ uint32_t val;
+ int retval;
+ const uint8_t origninal_ap = dap->ap_current;
+
+ dap_ap_select(dap, 1);
+
+
+ /*
+ * ... The MDM-AP ID register can be read to verify that the
+ * connection is working correctly...
+ */
+ retval = kinetis_mdm_read_register(dap, MDM_REG_ID, &val);
+ if (retval != ERROR_OK) {
+ LOG_ERROR("MDM: failed to read ID register");
+ goto fail;
+ }
+
+ bool found = false;
+ for (size_t i = 0; i < ARRAY_SIZE(kinetis_known_mdm_ids); i++) {
+ if (val == kinetis_known_mdm_ids[i]) {
+ found = true;
+ break;
+ }
+ }
+
+ if (!found)
+ LOG_WARNING("MDM: unknown ID %08" PRIX32, val);
+
+ /*
+ * ... Read the MDM-AP status register until the Flash Ready bit sets...
+ */
+ retval = kinetis_mdm_poll_register(dap, MDM_REG_STAT,
+ MDM_STAT_FREADY,
+ MDM_STAT_FREADY);
+ if (retval != ERROR_OK) {
+ LOG_ERROR("MDM: flash ready timeout");
+ goto fail;
+ }
+
+ /*
+ * ... Read the System Security bit to determine if security is enabled.
+ * If System Security = 0, then proceed. If System Security = 1, then
+ * communication with the internals of the processor, including the
+ * flash, will not be possible without issuing a mass erase command or
+ * unsecuring the part through other means (backdoor key unlock)...
+ */
+ retval = kinetis_mdm_read_register(dap, MDM_REG_STAT, &val);
+ if (retval != ERROR_OK) {
+ LOG_ERROR("MDM: failed to read MDM_REG_STAT");
+ goto fail;
+ }
+
+ if (val & MDM_STAT_SYSSEC) {
+ jtag_poll_set_enabled(false);
+
+ LOG_WARNING("*********** ATTENTION! ATTENTION! ATTENTION! ATTENTION! **********");
+ LOG_WARNING("**** ****");
+ LOG_WARNING("**** Your Kinetis MCU is in secured state, which means that, ****");
+ LOG_WARNING("**** with exception for very basic communication, JTAG/SWD ****");
+ LOG_WARNING("**** interface will NOT work. In order to restore its ****");
+ LOG_WARNING("**** functionality please issue 'kinetis mdm mass_erase' ****");
+ LOG_WARNING("**** command, power cycle the MCU and restart OpenOCD. ****");
+ LOG_WARNING("**** ****");
+ LOG_WARNING("*********** ATTENTION! ATTENTION! ATTENTION! ATTENTION! **********");
+ } else {
+ LOG_INFO("MDM: Chip is unsecured. Continuing.");
+ jtag_poll_set_enabled(true);
+ }
+
+ dap_ap_select(dap, origninal_ap);
+
+ return ERROR_OK;
+
+fail:
+ LOG_ERROR("MDM: Failed to check security status of the MCU. Cannot proceed further");
+ jtag_poll_set_enabled(false);
+ return retval;
+}
+
FLASH_BANK_COMMAND_HANDLER(kinetis_flash_bank_command)
{
struct kinetis_flash_bank *bank_info;
return ERROR_OK;
}
-static int kinetis_mass_erase(struct flash_bank *bank)
+COMMAND_HANDLER(kinetis_securing_test)
{
int result;
uint8_t ftfx_fstat;
+ struct target *target = get_current_target(CMD_CTX);
+ struct flash_bank *bank = NULL;
- if (bank->target->state != TARGET_HALTED) {
+ result = get_flash_bank_by_addr(target, 0x00000000, true, &bank);
+ if (result != ERROR_OK)
+ return result;
+
+ assert(bank != NULL);
+
+ if (target->state != TARGET_HALTED) {
LOG_ERROR("Target not halted");
return ERROR_TARGET_NOT_HALTED;
}
- /* check if whole bank is blank */
- LOG_INFO("Execute Erase All Blocks");
- /* set command and sector address */
- result = kinetis_ftfx_command(bank, FTFx_CMD_MASSERASE, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, &ftfx_fstat);
- /* Anyway Result, write FSEC to unsecure forcely */
- /* if (result != ERROR_OK)
- return result;*/
-
- /* Write to MCU security status unsecure in Flash security byte(for Kinetis-L need) */
- LOG_INFO("Write to MCU security status unsecure Anyway!");
- uint8_t padding[4] = {0xFE, 0xFF, 0xFF, 0xFF}; /* Write 0xFFFFFFFE */
-
- result = kinetis_ftfx_command(bank, FTFx_CMD_LWORDPROG, (bank->base + 0x0000040C),
- padding[3], padding[2], padding[1], padding[0],
- 0, 0, 0, 0, &ftfx_fstat);
- if (result != ERROR_OK)
- return ERROR_FLASH_OPERATION_FAILED;
-
- return ERROR_OK;
+ return kinetis_ftfx_command(bank, FTFx_CMD_SECTERASE, bank->base + 0x00000400,
+ 0, 0, 0, 0, 0, 0, 0, 0, &ftfx_fstat);
}
static int kinetis_erase(struct flash_bank *bank, int first, int last)
if ((first > bank->num_sectors) || (last > bank->num_sectors))
return ERROR_FLASH_OPERATION_FAILED;
- if ((first == 0) && (last == (bank->num_sectors - 1)))
- return kinetis_mass_erase(bank);
-
/*
* FIXME: TODO: use the 'Erase Flash Block' command if the
* requested erase is PFlash or NVM and encompasses the entire
return ERROR_TARGET_NOT_HALTED;
}
- if (kinfo->klxx) {
+ if (!(kinfo->flash_support & FS_PROGRAM_SECTOR)) {
/* fallback to longword write */
fallback = 1;
- LOG_WARNING("Kinetis L Series supports Program Longword execution only.");
+ LOG_WARNING("This device supports Program Longword execution only.");
LOG_DEBUG("flash write into PFLASH @08%" PRIX32, offset);
} else if (kinfo->flash_class == FC_FLEX_NVM) {
* Kinetis "chunk" is 16 bytes (128 bits).
*/
unsigned prog_section_chunk_bytes = kinfo->sector_size >> 8;
- /* assume the NVM sector size is half the FlexRAM size */
- unsigned prog_size_bytes = MIN(kinfo->sector_size,
- kinetis_flash_params[kinfo->granularity].nvm_sector_size_bytes);
+ unsigned prog_size_bytes = kinfo->max_flash_prog_size;
for (i = 0; i < count; i += prog_size_bytes) {
uint8_t residual_buffer[16];
uint8_t ftfx_fstat;
}
}
/* program longword command, not supported in "SF3" devices */
- else if ((kinfo->granularity != 3) || (kinfo->klxx)) {
-
+ else if (kinfo->flash_support & FS_PROGRAM_LONGWORD) {
if (count & 0x3) {
uint32_t old_count = count;
count = (old_count | 3) + 1;
return ERROR_FLASH_OPERATION_FAILED;
}
}
-
} else {
LOG_ERROR("Flash write strategy not implemented");
return ERROR_FLASH_OPERATION_FAILED;
uint32_t offset = 0;
uint8_t fcfg1_nvmsize, fcfg1_pfsize, fcfg1_eesize, fcfg2_pflsh;
uint32_t nvm_size = 0, pf_size = 0, ee_size = 0;
- unsigned granularity, num_blocks = 0, num_pflash_blocks = 0, num_nvm_blocks = 0,
- first_nvm_bank = 0, reassign = 0;
+ unsigned num_blocks = 0, num_pflash_blocks = 0, num_nvm_blocks = 0, first_nvm_bank = 0,
+ reassign = 0, pflash_sector_size_bytes = 0, nvm_sector_size_bytes = 0;
struct target *target = bank->target;
struct kinetis_flash_bank *kinfo = bank->driver_priv;
if (result != ERROR_OK)
return result;
- kinfo->klxx = 0;
-
- /* K-series MCU? */
if ((kinfo->sim_sdid & (~KINETIS_SDID_K_SERIES_MASK)) == 0) {
+ /* older K-series MCU */
uint32_t mcu_type = kinfo->sim_sdid & KINETIS_K_SDID_TYPE_MASK;
switch (mcu_type) {
case KINETIS_K_SDID_K10_M50:
case KINETIS_K_SDID_K20_M50:
/* 1kB sectors */
- granularity = 0;
+ pflash_sector_size_bytes = 1<<10;
+ nvm_sector_size_bytes = 1<<10;
+ num_blocks = 2;
+ kinfo->flash_support = FS_PROGRAM_LONGWORD | FS_PROGRAM_SECTOR;
+ kinfo->max_flash_prog_size = 1<<10;
break;
case KINETIS_K_SDID_K10_M72:
case KINETIS_K_SDID_K20_M72:
case KINETIS_K_SDID_K40_M100:
case KINETIS_K_SDID_K50_M72:
/* 2kB sectors, 1kB FlexNVM sectors */
- granularity = 1;
+ pflash_sector_size_bytes = 2<<10;
+ nvm_sector_size_bytes = 1<<10;
+ num_blocks = 2;
+ kinfo->flash_support = FS_PROGRAM_LONGWORD | FS_PROGRAM_SECTOR;
+ kinfo->max_flash_prog_size = 1<<10;
break;
case KINETIS_K_SDID_K10_M100:
case KINETIS_K_SDID_K20_M100:
case KINETIS_K_SDID_K53:
case KINETIS_K_SDID_K60_M100:
/* 2kB sectors */
- granularity = 2;
+ pflash_sector_size_bytes = 2<<10;
+ nvm_sector_size_bytes = 2<<10;
+ num_blocks = 2;
+ kinfo->flash_support = FS_PROGRAM_LONGWORD | FS_PROGRAM_SECTOR;
+ kinfo->max_flash_prog_size = 2<<10;
break;
case KINETIS_K_SDID_K10_M120:
case KINETIS_K_SDID_K20_M120:
case KINETIS_K_SDID_K60_M150:
case KINETIS_K_SDID_K70_M150:
/* 4kB sectors */
- granularity = 3;
+ pflash_sector_size_bytes = 4<<10;
+ nvm_sector_size_bytes = 4<<10;
+ num_blocks = 4;
+ kinfo->flash_support = FS_PROGRAM_PHRASE | FS_PROGRAM_SECTOR;
+ kinfo->max_flash_prog_size = 4<<10;
break;
default:
LOG_ERROR("Unsupported K-family FAMID");
return ERROR_FLASH_OPER_UNSUPPORTED;
}
- }
- /* KL-series? */
- else if ((kinfo->sim_sdid & KINETIS_KL_SDID_SERIESID_MASK) == KINETIS_KL_SDID_SERIESID_KL) {
- kinfo->klxx = 1;
- granularity = 0;
} else {
+ /* Newer K-series or KL series MCU */
+ switch (kinfo->sim_sdid & KINETIS_SDID_SERIESID_MASK) {
+ case KINETIS_SDID_SERIESID_K:
+ switch (kinfo->sim_sdid & (KINETIS_SDID_FAMILYID_MASK | KINETIS_SDID_SUBFAMID_MASK)) {
+ case KINETIS_SDID_FAMILYID_K2X | KINETIS_SDID_SUBFAMID_KX2: {
+ /* MK24FN1M reports as K22, this should detect it (according to errata note 1N83J) */
+ uint32_t sopt1;
+ result = target_read_u32(target, SIM_SOPT1, &sopt1);
+ if (result != ERROR_OK)
+ return result;
+
+ if (((kinfo->sim_sdid & (KINETIS_SDID_DIEID_MASK)) == KINETIS_SDID_DIEID_K24FN1M) &&
+ ((sopt1 & KINETIS_SOPT1_RAMSIZE_MASK) == KINETIS_SOPT1_RAMSIZE_K24FN1M)) {
+ /* MK24FN1M */
+ pflash_sector_size_bytes = 4<<10;
+ num_blocks = 2;
+ kinfo->flash_support = FS_PROGRAM_PHRASE | FS_PROGRAM_SECTOR;
+ kinfo->max_flash_prog_size = 1<<10;
+ } else {
+ /* K22 with new-style SDID? */
+ break;
+ }
+ break;
+ }
+ case KINETIS_SDID_FAMILYID_K2X | KINETIS_SDID_SUBFAMID_KX4:
+ /* K24FN256 */
+ pflash_sector_size_bytes = 4<<10;
+ num_blocks = 1;
+ kinfo->flash_support = FS_PROGRAM_LONGWORD;
+ kinfo->max_flash_prog_size = 1<<10;
+ break;
+ default:
+ break;
+ }
+ break;
+ case KINETIS_SDID_SERIESID_KL:
+ /* KL-series */
+ pflash_sector_size_bytes = 1<<10;
+ nvm_sector_size_bytes = 1<<10;
+ num_blocks = 1;
+ kinfo->flash_support = FS_PROGRAM_LONGWORD;
+ kinfo->max_flash_prog_size = 1<<10;
+ break;
+ default:
+ break;
+ }
+ }
+
+ if (pflash_sector_size_bytes == 0) {
LOG_ERROR("MCU is unsupported");
return ERROR_FLASH_OPER_UNSUPPORTED;
}
nvm_size = 1 << (14 + (fcfg1_nvmsize >> 1));
break;
case 0x0f:
- if (granularity == 3)
+ if (pflash_sector_size_bytes >= 4<<10)
nvm_size = 512<<10;
else
+ /* K20_100 */
nvm_size = 256<<10;
break;
default:
pf_size = 1 << (14 + (fcfg1_pfsize >> 1));
break;
case 0x0f:
- if (granularity == 3)
+ if (pflash_sector_size_bytes >= 4<<10)
pf_size = 1024<<10;
else if (fcfg2_pflsh)
pf_size = 512<<10;
LOG_DEBUG("FlexNVM: %" PRIu32 " PFlash: %" PRIu32 " FlexRAM: %" PRIu32 " PFLSH: %d",
nvm_size, pf_size, ee_size, fcfg2_pflsh);
- if (kinfo->klxx)
- num_blocks = 1;
- else
- num_blocks = kinetis_flash_params[granularity].num_blocks;
num_pflash_blocks = num_blocks / (2 - fcfg2_pflsh);
first_nvm_bank = num_pflash_blocks;
if (kinfo->bank_ordinal != (unsigned) bank->bank_number) {
LOG_WARNING("Flash ordinal/bank number mismatch");
reassign = 1;
- } else if (kinfo->granularity != granularity) {
- LOG_WARNING("Flash granularity mismatch");
- reassign = 1;
} else {
switch (kinfo->flash_class) {
case FC_PFLASH:
(0x00000000 + bank->size * kinfo->bank_ordinal)) {
LOG_WARNING("PFlash address range mismatch");
reassign = 1;
- } else if (kinfo->sector_size !=
- kinetis_flash_params[granularity].pflash_sector_size_bytes) {
+ } else if (kinfo->sector_size != pflash_sector_size_bytes) {
LOG_WARNING("PFlash sector size mismatch");
reassign = 1;
} else {
(0x10000000 + bank->size * kinfo->bank_ordinal)) {
LOG_WARNING("FlexNVM address range mismatch");
reassign = 1;
- } else if (kinfo->sector_size !=
- kinetis_flash_params[granularity].nvm_sector_size_bytes) {
+ } else if (kinfo->sector_size != nvm_sector_size_bytes) {
LOG_WARNING("FlexNVM sector size mismatch");
reassign = 1;
} else {
} else if (bank->base != FLEXRAM) {
LOG_WARNING("FlexRAM address mismatch");
reassign = 1;
- } else if (kinfo->sector_size !=
- kinetis_flash_params[granularity].nvm_sector_size_bytes) {
+ } else if (kinfo->sector_size != nvm_sector_size_bytes) {
LOG_WARNING("FlexRAM sector size mismatch");
reassign = 1;
} else {
if (!reassign)
return ERROR_OK;
- kinfo->granularity = granularity;
-
if ((unsigned)bank->bank_number < num_pflash_blocks) {
/* pflash, banks start at address zero */
kinfo->flash_class = FC_PFLASH;
bank->size = (pf_size / num_pflash_blocks);
bank->base = 0x00000000 + bank->size * bank->bank_number;
- kinfo->sector_size = kinetis_flash_params[granularity].pflash_sector_size_bytes;
+ kinfo->sector_size = pflash_sector_size_bytes;
kinfo->protection_size = pf_size / 32;
} else if ((unsigned)bank->bank_number < num_blocks) {
/* nvm, banks start at address 0x10000000 */
kinfo->flash_class = FC_FLEX_NVM;
bank->size = (nvm_size / num_nvm_blocks);
bank->base = 0x10000000 + bank->size * (bank->bank_number - first_nvm_bank);
- kinfo->sector_size = kinetis_flash_params[granularity].nvm_sector_size_bytes;
+ kinfo->sector_size = nvm_sector_size_bytes;
kinfo->protection_size = 0; /* FIXME: TODO: depends on DEPART bits, chip */
} else if ((unsigned)bank->bank_number == num_blocks) {
LOG_ERROR("FlexRAM support not yet implemented");
return ERROR_OK;
}
+static const struct command_registration kinetis_securtiy_command_handlers[] = {
+ {
+ .name = "check_security",
+ .mode = COMMAND_EXEC,
+ .help = "",
+ .usage = "",
+ .handler = kinetis_check_flash_security_status,
+ },
+ {
+ .name = "mass_erase",
+ .mode = COMMAND_EXEC,
+ .help = "",
+ .usage = "",
+ .handler = kinetis_mdm_mass_erase,
+ },
+ {
+ .name = "test_securing",
+ .mode = COMMAND_EXEC,
+ .help = "",
+ .usage = "",
+ .handler = kinetis_securing_test,
+ },
+ COMMAND_REGISTRATION_DONE
+};
+
+static const struct command_registration kinetis_exec_command_handlers[] = {
+ {
+ .name = "mdm",
+ .mode = COMMAND_ANY,
+ .help = "",
+ .usage = "",
+ .chain = kinetis_securtiy_command_handlers,
+ },
+ COMMAND_REGISTRATION_DONE
+};
+
+static const struct command_registration kinetis_command_handler[] = {
+ {
+ .name = "kinetis",
+ .mode = COMMAND_ANY,
+ .help = "kinetis NAND flash controller commands",
+ .usage = "",
+ .chain = kinetis_exec_command_handlers,
+ },
+ COMMAND_REGISTRATION_DONE
+};
+
+
+
struct flash_driver kinetis_flash = {
.name = "kinetis",
+ .commands = kinetis_command_handler,
.flash_bank_command = kinetis_flash_bank_command,
.erase = kinetis_erase,
.protect = kinetis_protect,
projects / fw / openocd / blobdiff