#include <target/armv7m.h>
#include <target/cortex_m.h>
-/* keep family IDs in decimal */
-#define EFM_FAMILY_ID_GECKO 71
#define EFM_FAMILY_ID_GIANT_GECKO 72
-#define EFM_FAMILY_ID_TINY_GECKO 73
#define EFM_FAMILY_ID_LEOPARD_GECKO 74
-#define EFM_FAMILY_ID_WONDER_GECKO 75
-#define EFM_FAMILY_ID_ZERO_GECKO 76
-#define EFM_FAMILY_ID_HAPPY_GECKO 77
-#define EZR_FAMILY_ID_WONDER_GECKO 120
-#define EZR_FAMILY_ID_LEOPARD_GECKO 121
-#define EZR_FAMILY_ID_HAPPY_GECKO 122
-#define EFR_FAMILY_ID_MIGHTY_GECKO 16
-#define EFR_FAMILY_ID_BLUE_GECKO 20
#define EFM32_FLASH_ERASE_TMO 100
#define EFM32_FLASH_WDATAREADY_TMO 100
#define EFM32_MSC_LOCK_BITS (EFM32_MSC_INFO_BASE+0x4000)
#define EFM32_MSC_DEV_INFO (EFM32_MSC_INFO_BASE+0x8000)
-/* PAGE_SIZE is only present in Leopard, Giant and Wonder Gecko MCUs */
+/* PAGE_SIZE is not present in Zero, Happy and the original Gecko MCU */
#define EFM32_MSC_DI_PAGE_SIZE (EFM32_MSC_DEV_INFO+0x1e7)
#define EFM32_MSC_DI_FLASH_SZ (EFM32_MSC_DEV_INFO+0x1f8)
#define EFM32_MSC_DI_RAM_SZ (EFM32_MSC_DEV_INFO+0x1fa)
#define EFM32_MSC_DI_PROD_REV (EFM32_MSC_DEV_INFO+0x1ff)
#define EFM32_MSC_REGBASE 0x400c0000
-#define EFR32_MSC_REGBASE 0x400e0000
+#define EFM32_MSC_REGBASE_SERIES1 0x400e0000
#define EFM32_MSC_REG_WRITECTRL 0x008
#define EFM32_MSC_WRITECTRL_WREN_MASK 0x1
#define EFM32_MSC_REG_WRITECMD 0x00c
#define EFM32_MSC_STATUS_WORDTIMEOUT_MASK 0x10
#define EFM32_MSC_STATUS_ERASEABORTED_MASK 0x20
#define EFM32_MSC_REG_LOCK 0x03c
-#define EFR32_MSC_REG_LOCK 0x040
+#define EFM32_MSC_REG_LOCK_SERIES1 0x040
#define EFM32_MSC_LOCK_LOCKKEY 0x1b71
+struct efm32_family_data {
+ int family_id;
+ const char *name;
+
+ /* EFM32 series (EFM32LG995F is the "old" series 0, while EFR32MG12P132
+ is the "new" series 1). Determines location of MSC registers. */
+ int series;
+
+ /* Page size in bytes, or 0 to read from EFM32_MSC_DI_PAGE_SIZE */
+ int page_size;
+
+ /* MSC register base address, or 0 to use default */
+ uint32_t msc_regbase;
+};
+
struct efm32x_flash_bank {
- int probed;
+ bool probed;
uint32_t lb_page[LOCKBITS_PAGE_SZ/4];
uint32_t reg_base;
uint32_t reg_lock;
};
struct efm32_info {
+ const struct efm32_family_data *family_data;
uint16_t flash_sz_kib;
uint16_t ram_sz_kib;
uint16_t part_num;
uint16_t page_size;
};
+static const struct efm32_family_data efm32_families[] = {
+ { 16, "EFR32MG1P Mighty", .series = 1 },
+ { 17, "EFR32MG1B Mighty", .series = 1 },
+ { 18, "EFR32MG1V Mighty", .series = 1 },
+ { 19, "EFR32MG1P Blue", .series = 1 },
+ { 20, "EFR32MG1B Blue", .series = 1 },
+ { 21, "EFR32MG1V Blue", .series = 1 },
+ { 25, "EFR32FG1P Flex", .series = 1 },
+ { 26, "EFR32FG1B Flex", .series = 1 },
+ { 27, "EFR32FG1V Flex", .series = 1 },
+ { 28, "EFR32MG2P Mighty", .series = 1 },
+ { 29, "EFR32MG2B Mighty", .series = 1 },
+ { 30, "EFR32MG2V Mighty", .series = 1 },
+ { 31, "EFR32BG12P Blue", .series = 1 },
+ { 32, "EFR32BG12B Blue", .series = 1 },
+ { 33, "EFR32BG12V Blue", .series = 1 },
+ { 37, "EFR32FG12P Flex", .series = 1 },
+ { 38, "EFR32FG12B Flex", .series = 1 },
+ { 39, "EFR32FG12V Flex", .series = 1 },
+ { 40, "EFR32MG13P Mighty", .series = 1 },
+ { 41, "EFR32MG13B Mighty", .series = 1 },
+ { 42, "EFR32MG13V Mighty", .series = 1 },
+ { 43, "EFR32BG13P Blue", .series = 1 },
+ { 44, "EFR32BG13B Blue", .series = 1 },
+ { 45, "EFR32BG13V Blue", .series = 1 },
+ { 46, "EFR32ZG13P Zen", .series = 1 },
+ { 49, "EFR32FG13P Flex", .series = 1 },
+ { 50, "EFR32FG13B Flex", .series = 1 },
+ { 51, "EFR32FG13V Flex", .series = 1 },
+ { 52, "EFR32MG14P Mighty", .series = 1 },
+ { 53, "EFR32MG14B Mighty", .series = 1 },
+ { 54, "EFR32MG14V Mighty", .series = 1 },
+ { 55, "EFR32BG14P Blue", .series = 1 },
+ { 56, "EFR32BG14B Blue", .series = 1 },
+ { 57, "EFR32BG14V Blue", .series = 1 },
+ { 58, "EFR32ZG14P Zen", .series = 1 },
+ { 61, "EFR32FG14P Flex", .series = 1 },
+ { 62, "EFR32FG14B Flex", .series = 1 },
+ { 63, "EFR32FG14V Flex", .series = 1 },
+ { 71, "EFM32G", .series = 0, .page_size = 512 },
+ { 72, "EFM32GG Giant", .series = 0 },
+ { 73, "EFM32TG Tiny", .series = 0, .page_size = 512 },
+ { 74, "EFM32LG Leopard", .series = 0 },
+ { 75, "EFM32WG Wonder", .series = 0 },
+ { 76, "EFM32ZG Zero", .series = 0, .page_size = 1024 },
+ { 77, "EFM32HG Happy", .series = 0, .page_size = 1024 },
+ { 81, "EFM32PG1B Pearl", .series = 1 },
+ { 83, "EFM32JG1B Jade", .series = 1 },
+ { 85, "EFM32PG12B Pearl", .series = 1 },
+ { 87, "EFM32JG12B Jade", .series = 1 },
+ { 89, "EFM32PG13B Pearl", .series = 1 },
+ { 91, "EFM32JG13B Jade", .series = 1 },
+ { 100, "EFM32GG11B Giant", .series = 1, .msc_regbase = 0x40000000 },
+ { 103, "EFM32TG11B Tiny", .series = 1, .msc_regbase = 0x40000000 },
+ { 106, "EFM32GG12B Giant", .series = 1, .msc_regbase = 0x40000000 },
+ { 120, "EZR32WG Wonder", .series = 0 },
+ { 121, "EZR32LG Leopard", .series = 0 },
+ { 122, "EZR32HG Happy", .series = 0, .page_size = 1024 },
+};
+
+
static int efm32x_write(struct flash_bank *bank, const uint8_t *buffer,
uint32_t offset, uint32_t count);
memset(efm32_info, 0, sizeof(struct efm32_info));
ret = target_read_u32(bank->target, CPUID, &cpuid);
- if (ERROR_OK != ret)
+ if (ret != ERROR_OK)
return ret;
if (((cpuid >> 4) & 0xfff) == 0xc23) {
}
ret = efm32x_get_flash_size(bank, &(efm32_info->flash_sz_kib));
- if (ERROR_OK != ret)
+ if (ret != ERROR_OK)
return ret;
ret = efm32x_get_ram_size(bank, &(efm32_info->ram_sz_kib));
- if (ERROR_OK != ret)
+ if (ret != ERROR_OK)
return ret;
ret = efm32x_get_part_num(bank, &(efm32_info->part_num));
- if (ERROR_OK != ret)
+ if (ret != ERROR_OK)
return ret;
ret = efm32x_get_part_family(bank, &(efm32_info->part_family));
- if (ERROR_OK != ret)
+ if (ret != ERROR_OK)
return ret;
ret = efm32x_get_prod_rev(bank, &(efm32_info->prod_rev));
- if (ERROR_OK != ret)
+ if (ret != ERROR_OK)
return ret;
- if (EFR_FAMILY_ID_BLUE_GECKO == efm32_info->part_family ||
- EFR_FAMILY_ID_MIGHTY_GECKO == efm32_info->part_family) {
- efm32x_info->reg_base = EFR32_MSC_REGBASE;
- efm32x_info->reg_lock = EFR32_MSC_REG_LOCK;
- } else {
- efm32x_info->reg_base = EFM32_MSC_REGBASE;
- efm32x_info->reg_lock = EFM32_MSC_REG_LOCK;
+ for (size_t i = 0; i < ARRAY_SIZE(efm32_families); i++) {
+ if (efm32_families[i].family_id == efm32_info->part_family)
+ efm32_info->family_data = &efm32_families[i];
}
- if (EFM_FAMILY_ID_GECKO == efm32_info->part_family ||
- EFM_FAMILY_ID_TINY_GECKO == efm32_info->part_family)
- efm32_info->page_size = 512;
- else if (EFM_FAMILY_ID_ZERO_GECKO == efm32_info->part_family ||
- EFM_FAMILY_ID_HAPPY_GECKO == efm32_info->part_family ||
- EZR_FAMILY_ID_HAPPY_GECKO == efm32_info->part_family)
- efm32_info->page_size = 1024;
- else if (EFM_FAMILY_ID_GIANT_GECKO == efm32_info->part_family ||
- EFM_FAMILY_ID_LEOPARD_GECKO == efm32_info->part_family) {
- if (efm32_info->prod_rev >= 18) {
- uint8_t pg_size = 0;
- ret = target_read_u8(bank->target, EFM32_MSC_DI_PAGE_SIZE,
- &pg_size);
- if (ERROR_OK != ret)
- return ret;
-
- efm32_info->page_size = (1 << ((pg_size+10) & 0xff));
- } else {
- /* EFM32 GG/LG errata: MEM_INFO_PAGE_SIZE is invalid
- for MCUs with PROD_REV < 18 */
- if (efm32_info->flash_sz_kib < 512)
- efm32_info->page_size = 2048;
- else
- efm32_info->page_size = 4096;
- }
-
- if ((2048 != efm32_info->page_size) &&
- (4096 != efm32_info->page_size)) {
- LOG_ERROR("Invalid page size %u", efm32_info->page_size);
- return ERROR_FAIL;
- }
- } else if (EFM_FAMILY_ID_WONDER_GECKO == efm32_info->part_family ||
- EZR_FAMILY_ID_WONDER_GECKO == efm32_info->part_family ||
- EZR_FAMILY_ID_LEOPARD_GECKO == efm32_info->part_family ||
- EFR_FAMILY_ID_BLUE_GECKO == efm32_info->part_family ||
- EFR_FAMILY_ID_MIGHTY_GECKO == efm32_info->part_family) {
- uint8_t pg_size = 0;
- ret = target_read_u8(bank->target, EFM32_MSC_DI_PAGE_SIZE,
- &pg_size);
- if (ERROR_OK != ret)
- return ret;
-
- efm32_info->page_size = (1 << ((pg_size+10) & 0xff));
- if (2048 != efm32_info->page_size) {
- LOG_ERROR("Invalid page size %u", efm32_info->page_size);
- return ERROR_FAIL;
- }
- } else {
+ if (!efm32_info->family_data) {
LOG_ERROR("Unknown MCU family %d", efm32_info->part_family);
return ERROR_FAIL;
}
- return ERROR_OK;
-}
-
-/*
- * Helper to create a human friendly string describing a part
- */
-static int efm32x_decode_info(struct efm32_info *info, char *buf, int buf_size)
-{
- int printed = 0;
-
- switch (info->part_family) {
- case EZR_FAMILY_ID_WONDER_GECKO:
- case EZR_FAMILY_ID_LEOPARD_GECKO:
- case EZR_FAMILY_ID_HAPPY_GECKO:
- printed = snprintf(buf, buf_size, "EZR32 ");
+ switch (efm32_info->family_data->series) {
+ case 0:
+ efm32x_info->reg_base = EFM32_MSC_REGBASE;
+ efm32x_info->reg_lock = EFM32_MSC_REG_LOCK;
break;
- case EFR_FAMILY_ID_MIGHTY_GECKO:
- case EFR_FAMILY_ID_BLUE_GECKO:
- printed = snprintf(buf, buf_size, "EFR32 ");
+ case 1:
+ efm32x_info->reg_base = EFM32_MSC_REGBASE_SERIES1;
+ efm32x_info->reg_lock = EFM32_MSC_REG_LOCK_SERIES1;
break;
- default:
- printed = snprintf(buf, buf_size, "EFM32 ");
}
- buf += printed;
- buf_size -= printed;
-
- if (0 >= buf_size)
- return ERROR_BUF_TOO_SMALL;
-
- switch (info->part_family) {
- case EFM_FAMILY_ID_GECKO:
- printed = snprintf(buf, buf_size, "Gecko");
- break;
- case EFM_FAMILY_ID_GIANT_GECKO:
- printed = snprintf(buf, buf_size, "Giant Gecko");
- break;
- case EFM_FAMILY_ID_TINY_GECKO:
- printed = snprintf(buf, buf_size, "Tiny Gecko");
- break;
- case EFM_FAMILY_ID_LEOPARD_GECKO:
- case EZR_FAMILY_ID_LEOPARD_GECKO:
- printed = snprintf(buf, buf_size, "Leopard Gecko");
- break;
- case EFM_FAMILY_ID_WONDER_GECKO:
- case EZR_FAMILY_ID_WONDER_GECKO:
- printed = snprintf(buf, buf_size, "Wonder Gecko");
- break;
- case EFM_FAMILY_ID_ZERO_GECKO:
- printed = snprintf(buf, buf_size, "Zero Gecko");
- break;
- case EFM_FAMILY_ID_HAPPY_GECKO:
- case EZR_FAMILY_ID_HAPPY_GECKO:
- printed = snprintf(buf, buf_size, "Happy Gecko");
- break;
- case EFR_FAMILY_ID_BLUE_GECKO:
- printed = snprintf(buf, buf_size, "Blue Gecko");
- break;
- case EFR_FAMILY_ID_MIGHTY_GECKO:
- printed = snprintf(buf, buf_size, "Mighty Gecko");
- break;
- }
+ if (efm32_info->family_data->msc_regbase != 0)
+ efm32x_info->reg_base = efm32_info->family_data->msc_regbase;
- buf += printed;
- buf_size -= printed;
+ if (efm32_info->family_data->page_size != 0) {
+ efm32_info->page_size = efm32_info->family_data->page_size;
+ } else {
+ uint8_t pg_size = 0;
+ ret = target_read_u8(bank->target, EFM32_MSC_DI_PAGE_SIZE,
+ &pg_size);
+ if (ret != ERROR_OK)
+ return ret;
- if (0 >= buf_size)
- return ERROR_BUF_TOO_SMALL;
+ efm32_info->page_size = (1 << ((pg_size+10) & 0xff));
- printed = snprintf(buf, buf_size, " - Rev: %d", info->prod_rev);
- buf += printed;
- buf_size -= printed;
+ if (efm32_info->part_family == EFM_FAMILY_ID_GIANT_GECKO ||
+ efm32_info->part_family == EFM_FAMILY_ID_LEOPARD_GECKO) {
+ /* Giant or Leopard Gecko */
+ if (efm32_info->prod_rev < 18) {
+ /* EFM32 GG/LG errata: MEM_INFO_PAGE_SIZE is invalid
+ for MCUs with PROD_REV < 18 */
+ if (efm32_info->flash_sz_kib < 512)
+ efm32_info->page_size = 2048;
+ else
+ efm32_info->page_size = 4096;
+ }
+ }
- if (0 >= buf_size)
- return ERROR_BUF_TOO_SMALL;
+ if ((efm32_info->page_size != 2048) &&
+ (efm32_info->page_size != 4096)) {
+ LOG_ERROR("Invalid page size %u", efm32_info->page_size);
+ return ERROR_FAIL;
+ }
+ }
return ERROR_OK;
}
-/* flash bank efm32 <base> <size> 0 0 <target#>
- */
+/* flash bank efm32 <base> <size> 0 0 <target#> */
FLASH_BANK_COMMAND_HANDLER(efm32x_flash_bank_command)
{
struct efm32x_flash_bank *efm32x_info;
efm32x_info = malloc(sizeof(struct efm32x_flash_bank));
bank->driver_priv = efm32x_info;
- efm32x_info->probed = 0;
+ efm32x_info->probed = false;
memset(efm32x_info->lb_page, 0xff, LOCKBITS_PAGE_SZ);
return ERROR_OK;
uint32_t reg_val = 0;
ret = efm32x_read_reg_u32(bank, reg, ®_val);
- if (ERROR_OK != ret)
+ if (ret != ERROR_OK)
return ret;
if (set)
while (1) {
ret = efm32x_read_reg_u32(bank, EFM32_MSC_REG_STATUS, &status);
- if (ERROR_OK != ret)
+ if (ret != ERROR_OK)
break;
LOG_DEBUG("status: 0x%" PRIx32 "", status);
- if (((status & wait_mask) == 0) && (0 == wait_for_set))
+ if (((status & wait_mask) == 0) && (wait_for_set == 0))
break;
else if (((status & wait_mask) != 0) && wait_for_set)
break;
*/
int ret = 0;
uint32_t status = 0;
-
+ addr += bank->base;
LOG_DEBUG("erasing flash page at 0x%08" PRIx32, addr);
ret = efm32x_write_reg_u32(bank, EFM32_MSC_REG_ADDRB, addr);
- if (ERROR_OK != ret)
+ if (ret != ERROR_OK)
return ret;
ret = efm32x_set_reg_bits(bank, EFM32_MSC_REG_WRITECMD,
EFM32_MSC_WRITECMD_LADDRIM_MASK, 1);
- if (ERROR_OK != ret)
+ if (ret != ERROR_OK)
return ret;
ret = efm32x_read_reg_u32(bank, EFM32_MSC_REG_STATUS, &status);
- if (ERROR_OK != ret)
+ if (ret != ERROR_OK)
return ret;
LOG_DEBUG("status 0x%" PRIx32, status);
ret = efm32x_set_reg_bits(bank, EFM32_MSC_REG_WRITECMD,
EFM32_MSC_WRITECMD_ERASEPAGE_MASK, 1);
- if (ERROR_OK != ret)
+ if (ret != ERROR_OK)
return ret;
return efm32x_wait_status(bank, EFM32_FLASH_ERASE_TMO,
EFM32_MSC_STATUS_BUSY_MASK, 0);
}
-static int efm32x_erase(struct flash_bank *bank, int first, int last)
+static int efm32x_erase(struct flash_bank *bank, unsigned int first,
+ unsigned int last)
{
struct target *target = bank->target;
- int i = 0;
int ret = 0;
- if (TARGET_HALTED != target->state) {
+ if (target->state != TARGET_HALTED) {
LOG_ERROR("Target not halted");
return ERROR_TARGET_NOT_HALTED;
}
efm32x_msc_lock(bank, 0);
ret = efm32x_set_wren(bank, 1);
- if (ERROR_OK != ret) {
+ if (ret != ERROR_OK) {
LOG_ERROR("Failed to enable MSC write");
return ret;
}
- for (i = first; i <= last; i++) {
+ for (unsigned int i = first; i <= last; i++) {
ret = efm32x_erase_page(bank, bank->sectors[i].offset);
- if (ERROR_OK != ret)
+ if (ret != ERROR_OK)
LOG_ERROR("Failed to erase page %d", i);
}
{
struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
struct target *target = bank->target;
- int i = 0;
int data_size = 0;
uint32_t *ptr = NULL;
int ret = 0;
ptr = efm32x_info->lb_page;
- for (i = 0; i < data_size; i++, ptr++) {
+ for (int i = 0; i < data_size; i++, ptr++) {
ret = target_read_u32(target, EFM32_MSC_LOCK_BITS+i*4, ptr);
- if (ERROR_OK != ret) {
+ if (ret != ERROR_OK) {
LOG_ERROR("Failed to read PLW %d", i);
return ret;
}
}
- /* also, read ULW, DLW and MLW */
+ /* also, read ULW, DLW, MLW, ALW and CLW words */
/* ULW, word 126 */
ptr = efm32x_info->lb_page + 126;
ret = target_read_u32(target, EFM32_MSC_LOCK_BITS+126*4, ptr);
- if (ERROR_OK != ret) {
+ if (ret != ERROR_OK) {
LOG_ERROR("Failed to read ULW");
return ret;
}
/* DLW, word 127 */
ptr = efm32x_info->lb_page + 127;
ret = target_read_u32(target, EFM32_MSC_LOCK_BITS+127*4, ptr);
- if (ERROR_OK != ret) {
+ if (ret != ERROR_OK) {
LOG_ERROR("Failed to read DLW");
return ret;
}
- /* MLW, word 125, present in GG and LG */
+ /* MLW, word 125, present in GG, LG, PG, JG, EFR32 */
ptr = efm32x_info->lb_page + 125;
ret = target_read_u32(target, EFM32_MSC_LOCK_BITS+125*4, ptr);
- if (ERROR_OK != ret) {
+ if (ret != ERROR_OK) {
LOG_ERROR("Failed to read MLW");
return ret;
}
+ /* ALW, word 124, present in GG, LG, PG, JG, EFR32 */
+ ptr = efm32x_info->lb_page + 124;
+ ret = target_read_u32(target, EFM32_MSC_LOCK_BITS+124*4, ptr);
+ if (ret != ERROR_OK) {
+ LOG_ERROR("Failed to read ALW");
+ return ret;
+ }
+
+ /* CLW1, word 123, present in EFR32 */
+ ptr = efm32x_info->lb_page + 123;
+ ret = target_read_u32(target, EFM32_MSC_LOCK_BITS+123*4, ptr);
+ if (ret != ERROR_OK) {
+ LOG_ERROR("Failed to read CLW1");
+ return ret;
+ }
+
+ /* CLW0, word 122, present in GG, LG, PG, JG, EFR32 */
+ ptr = efm32x_info->lb_page + 122;
+ ret = target_read_u32(target, EFM32_MSC_LOCK_BITS+122*4, ptr);
+ if (ret != ERROR_OK) {
+ LOG_ERROR("Failed to read CLW0");
+ return ret;
+ }
+
return ERROR_OK;
}
int ret = 0;
ret = efm32x_erase_page(bank, EFM32_MSC_LOCK_BITS);
- if (ERROR_OK != ret) {
+ if (ret != ERROR_OK) {
LOG_ERROR("Failed to erase LB page");
return ret;
}
return ERROR_OK;
}
-static int efm32x_protect(struct flash_bank *bank, int set, int first, int last)
+static int efm32x_protect(struct flash_bank *bank, int set, unsigned int first,
+ unsigned int last)
{
struct target *target = bank->target;
- int i = 0;
int ret = 0;
if (!set) {
return ERROR_TARGET_NOT_HALTED;
}
- for (i = first; i <= last; i++) {
+ for (unsigned int i = first; i <= last; i++) {
ret = efm32x_set_page_lock(bank, i, set);
- if (ERROR_OK != ret) {
+ if (ret != ERROR_OK) {
LOG_ERROR("Failed to set lock on page %d", i);
return ret;
}
}
ret = efm32x_write_lock_data(bank);
- if (ERROR_OK != ret) {
+ if (ret != ERROR_OK) {
LOG_ERROR("Failed to write LB page");
return ret;
}
keep_alive();
ret = efm32x_write_reg_u32(bank, EFM32_MSC_REG_ADDRB, addr);
- if (ERROR_OK != ret)
+ if (ret != ERROR_OK)
return ret;
ret = efm32x_set_reg_bits(bank, EFM32_MSC_REG_WRITECMD,
EFM32_MSC_WRITECMD_LADDRIM_MASK, 1);
- if (ERROR_OK != ret)
+ if (ret != ERROR_OK)
return ret;
ret = efm32x_read_reg_u32(bank, EFM32_MSC_REG_STATUS, &status);
- if (ERROR_OK != ret)
+ if (ret != ERROR_OK)
return ret;
LOG_DEBUG("status 0x%" PRIx32, status);
ret = efm32x_wait_status(bank, EFM32_FLASH_WDATAREADY_TMO,
EFM32_MSC_STATUS_WDATAREADY_MASK, 1);
- if (ERROR_OK != ret) {
+ if (ret != ERROR_OK) {
LOG_ERROR("Wait for WDATAREADY failed");
return ret;
}
ret = efm32x_write_reg_u32(bank, EFM32_MSC_REG_WDATA, val);
- if (ERROR_OK != ret) {
+ if (ret != ERROR_OK) {
LOG_ERROR("WDATA write failed");
return ret;
}
ret = efm32x_write_reg_u32(bank, EFM32_MSC_REG_WRITECMD,
EFM32_MSC_WRITECMD_WRITEONCE_MASK);
- if (ERROR_OK != ret) {
+ if (ret != ERROR_OK) {
LOG_ERROR("WRITECMD write failed");
return ret;
}
ret = efm32x_wait_status(bank, EFM32_FLASH_WRITE_TMO,
EFM32_MSC_STATUS_BUSY_MASK, 0);
- if (ERROR_OK != ret) {
+ if (ret != ERROR_OK) {
LOG_ERROR("Wait for BUSY failed");
return ret;
}
uint32_t old_count = count;
count = (old_count | 3) + 1;
new_buffer = malloc(count);
- if (new_buffer == NULL) {
+ if (!new_buffer) {
LOG_ERROR("odd number of bytes to write and no memory "
"for padding buffer");
return ERROR_FAIL;
retval = retval2;
cleanup:
- if (new_buffer)
- free(new_buffer);
-
+ free(new_buffer);
return retval;
}
struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
struct efm32_info efm32_mcu_info;
int ret;
- int i;
uint32_t base_address = 0x00000000;
- char buf[256];
- efm32x_info->probed = 0;
+ efm32x_info->probed = false;
memset(efm32x_info->lb_page, 0xff, LOCKBITS_PAGE_SZ);
ret = efm32x_read_info(bank, &efm32_mcu_info);
- if (ERROR_OK != ret)
- return ret;
-
- ret = efm32x_decode_info(&efm32_mcu_info, buf, sizeof(buf));
- if (ERROR_OK != ret)
+ if (ret != ERROR_OK)
return ret;
- LOG_INFO("detected part: %s", buf);
+ LOG_INFO("detected part: %s Gecko, rev %d",
+ efm32_mcu_info.family_data->name, efm32_mcu_info.prod_rev);
LOG_INFO("flash size = %dkbytes", efm32_mcu_info.flash_sz_kib);
LOG_INFO("flash page size = %dbytes", efm32_mcu_info.page_size);
- assert(0 != efm32_mcu_info.page_size);
+ assert(efm32_mcu_info.page_size != 0);
int num_pages = efm32_mcu_info.flash_sz_kib * 1024 /
efm32_mcu_info.page_size;
assert(num_pages > 0);
- if (bank->sectors) {
- free(bank->sectors);
- bank->sectors = NULL;
- }
+ free(bank->sectors);
+ bank->sectors = NULL;
bank->base = base_address;
bank->size = (num_pages * efm32_mcu_info.page_size);
bank->num_sectors = num_pages;
ret = efm32x_read_lock_data(bank);
- if (ERROR_OK != ret) {
+ if (ret != ERROR_OK) {
LOG_ERROR("Failed to read LB data");
return ret;
}
bank->sectors = malloc(sizeof(struct flash_sector) * num_pages);
- for (i = 0; i < num_pages; i++) {
+ for (int i = 0; i < num_pages; i++) {
bank->sectors[i].offset = i * efm32_mcu_info.page_size;
bank->sectors[i].size = efm32_mcu_info.page_size;
bank->sectors[i].is_erased = -1;
bank->sectors[i].is_protected = 1;
}
- efm32x_info->probed = 1;
+ efm32x_info->probed = true;
return ERROR_OK;
}
{
struct target *target = bank->target;
int ret = 0;
- int i = 0;
if (target->state != TARGET_HALTED) {
LOG_ERROR("Target not halted");
}
ret = efm32x_read_lock_data(bank);
- if (ERROR_OK != ret) {
+ if (ret != ERROR_OK) {
LOG_ERROR("Failed to read LB data");
return ret;
}
- assert(NULL != bank->sectors);
+ assert(bank->sectors);
- for (i = 0; i < bank->num_sectors; i++)
+ for (unsigned int i = 0; i < bank->num_sectors; i++)
bank->sectors[i].is_protected = efm32x_get_page_lock(bank, i);
return ERROR_OK;
}
-static int get_efm32x_info(struct flash_bank *bank, char *buf, int buf_size)
+static int get_efm32x_info(struct flash_bank *bank, struct command_invocation *cmd)
{
struct efm32_info info;
- int ret = 0;
+ int ret;
ret = efm32x_read_info(bank, &info);
- if (ERROR_OK != ret) {
+ if (ret != ERROR_OK) {
LOG_ERROR("Failed to read EFM32 info");
return ret;
}
- return efm32x_decode_info(&info, buf, buf_size);
+ command_print_sameline(cmd, "%s Gecko, rev %d", info.family_data->name, info.prod_rev);
+ return ERROR_OK;
}
COMMAND_HANDLER(efm32x_handle_debuglock_command)
struct flash_bank *bank;
int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
*ptr = 0;
retval = efm32x_write_lock_data(bank);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("Failed to write LB page");
return retval;
}
- command_print(CMD_CTX, "efm32x debug interface locked, reset the device to apply");
+ command_print(CMD, "efm32x debug interface locked, reset the device to apply");
return ERROR_OK;
}
COMMAND_REGISTRATION_DONE
};
-struct flash_driver efm32_flash = {
+const struct flash_driver efm32_flash = {
.name = "efm32",
.commands = efm32x_command_handlers,
.flash_bank_command = efm32x_flash_bank_command,
.erase_check = default_flash_blank_check,
.protect_check = efm32x_protect_check,
.info = get_efm32x_info,
+ .free_driver_priv = default_flash_free_driver_priv,
};
projects / fw / openocd / blobdiff